Bipolar circuit elements providing self-completion-indication. - Ted E. Williams; Mark Horowitz (IEEE J. Solid State Circuits, 1990)

A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. - Ted E. Williams; Mark A. Horowitz (IEEE Symposium on Computer Arithmetic, 1991)

A zero-overhead self-timed 160-ns 54-b CMOS divider. - Ted E. Williams; Mark A. Horowitz (IEEE J. Solid State Circuits, 1991)

Performance of iterative computation in self-timed rings. - Ted E. Williams (J. VLSI Signal Process., 1994)