A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2012)

A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2013)

A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2013)

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. - Teerachot Siriburanon; Takahiro Sato; Ahmed Musa; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. - Ahmed Musa; Wei Deng 001; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. - Teerachot Siriburanon; Tomohiro Ueno; Kento Kimura; Satoshi Kondo; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

An HDL-synthesized gated-edge-injection PLL with a current output DAC. - Dongsheng Yang 002; Wei Deng 001; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. - Teerachot Siriburanon; Hanli Liu; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. - Wei Deng 001; Dongsheng Yang 002; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Nurul Fajri; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Teerachot Siriburanon; Shoutarou Maki; Bangan Liu; Yun Wang 008; et al. (ISSCC, 2016)

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. - Teerachot Siriburanon; Satoshi Kondo; Makihiko Katsuragi; Hanli Liu; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (ASICON, 2017)

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Aravind Tharayil Narayanan; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. - Peng Chen 022; Feifei Zhang; Zhirui Zong; Hao Zheng; Teerachot Siriburanon; Robert Bogdan Staszewski (A-SSCC, 2017)

A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (ESSCIRC, 2017)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (IEEE J. Solid State Circuits, 2017)

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. - Hanli Liu; Teerachot Siriburanon; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2018)

A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS. - Naser Pourmousavian; Feng-Wei Kuo; Teerachot Siriburanon; Masoud Babaie; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2018)

DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. - Vivek Govindaraj; Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (APCCAS, 2019)

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. - Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (CICC, 2019)

A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip. - Imran Bashir; Krzysztof Pomorski; Robert Bogdan Staszewski; Mike Asker; Cagri Cetintepe; Dirk Leipold; Ali Esmailiyan; Hongying Wang; Teerachot Siriburanon; Panagiotis Giounanlis; Elena Blokhina (ESSCIRC, 2019)

A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2019)

28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. - Zhong Gao; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (NEWCAS, 2019)

A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. - Peng Chen 022; Feifei Zhang; Zhirui Zong; Suoping Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2019)

A 265- $ mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. - Hanli Liu; Atsushi Shirane; Kenichi Okada 001; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya (IEEE J. Solid State Circuits, 2019)

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (IEEE J. Solid State Circuits, 2019)

Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. - Pierre Bisiaux; Elena Blokhina; Eugene Koskin; Teerachot Siriburanon; Dimitri Galayko (ECCTD, 2020)

Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K. - Robert Bogdan Staszewski; Panagiotis Giounanlis; Ali Esmailiyan; Hongying Wang; Imran Bashir; Cagri Cetintepe; Dennis Andrade-Miceli; Mike Asker; Dirk Leipold; Teerachot Siriburanon; Andrii Sokolov; Elena Blokhina (ISCAS, 2020)

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Zhong Gao; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (ISSCC, 2020)

A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS. - Enis Kobal; Teerachot Siriburanon; Robert Bogdan Staszewski; Anding Zhu (ESSCIRC, 2021)

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. - Jianglin Du; Teerachot Siriburanon; Xi Chen 070; Yizhe Hu; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (VLSI Circuits, 2021)

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. - Jianglin Du; Teerachot Siriburanon; Yizhe Hu; Vivek Govindaraj; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

A Type-II Phase-Tracking Receiver. - Suoping Hu; Jianglin Du; Peng Chen 022; Hieu Minh Nguyen; Philip Quinlan; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. - Ali Esmailiyan; Jianglin Du; Teerachot Siriburanon; Filippo Schembari; Robert Bogdan Staszewski (IEEE Open J. Circuits Syst., 2021)

Oscillator Flicker Phase Noise: A Tutorial. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures. - Dennis Andrade-Miceli; Conor Power; Ali Esmailiyan; Teerachot Siriburanon; Imran Bashir; Mike Asker; Dirk Leipold; Robert Bogdan Staszewski; Elena Blokhina (ICECS 2022, 2022)

A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. - Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Enis Kobal; Philip Quinlan; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing. - Enis Kobal; Teerachot Siriburanon; Xi Chen 070; Hieu Minh Nguyen; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE J. Solid State Circuits, 2023)

A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications. - Enis Kobal; Teerachot Siriburanon; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS. - Ali Esmailiyan; Elena Blokhina; Dennis Andrade-Miceli; Eoin Faust; Panagiotis Giounanlis; Dirk Leipold; Hongying Wang; Imran Bashir; Eugene Koskin; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Tiny 3.15-43.4-GHz 3.6-mW Divide-by-8 Ring-Based Injection-Locked Frequency Divider Using Multiphase Waveform Gating Technique. - Feifan Hong; Xi Chen 070; Anding Zhu; Robert Bogdan Staszewski; Teerachot Siriburanon (A-SSCC, 2024)

A Mixer-BBPD-Based Real-Time I/Q Calibration Loop for High-Speed Ring-Oscillators. - Feifan Hong; Teerachot Siriburanon; Robert Bogdan Staszewski (ICTA, 2024)

Gauging the Capability of Artificial Intelligence Chatbot Tools to Answer Textbook Coursework Exercises in Circuit Design Education. - Yevhenii Mormul; Jan Przybyszewski; Teerachot Siriburanon; John Healy; Paul Cuffe (ITHET, 2024)

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling. - Sayan Kumar; Patchara Sawakewang; Teerachot Siriburanon; Robert Bogdan Staszewski (VLSI Technology and Circuits, 2024)

A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. - Pingda Guan; Ruichang Ma; Haikun Jia; Wei Deng 001; Mingxing Deng; Jiamin Xue; Angxiao Yan; Shiyan Sun; Qiuyu Peng; Teerachot Siriburanon; Robert Bogdan Staszewski; Zhihua Wang 001; et al. (IEEE J. Solid State Circuits, 2024)

Trifilar-Transformer-Coupled Series-Resonance Oscillator with Enhanced Tuning Range. - Sumit Dash; Sayan Kumar; Teerachot Siriburanon; Robert Bogdan Staszewski (ISCAS, 2025)

A Ring Temperature Sensor for Quantum Applications. - Ali Esmailiyan; Eugene Koskin; Dennis Andrade-Miceli; Andrii Sokolov; Teerachot Siriburanon; Dirk Leipold; David J. Redmond; Imran Bashir; Elena Blokhina; Robert Bogdan Staszewski (ISCAS, 2025)

A 0.012mm2 Inverter-Based Ring-Oscillator with Power-Supply Voltage Noise Isolator for Quantum Applications in 22-nm FD-SOI CMOS. - Ali Esmailiyan; Teerachot Siriburanon; Dennis Andrade-Miceli; Eugene Koskin; Dirk Leipold; David J. Redmond; Imran Bashir; Elena Blokhina; Robert Bogdan Staszewski (ISCAS, 2025)

A 4kb 4T eDRAM with Balanced Retention Time Adjustment. - Sayan Kumar; Dennis Andrade-Miceli; Chawin Khongprasongsiri; Teerachot Siriburanon; Robert Bogdan Staszewski (ISCAS, 2025)

19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz. - Jiawen Chen; Kai Xu; Teerachot Siriburanon; Robert Bogdan Staszewski (ISSCC, 2025)

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations. - Sayan Kumar; Teerachot Siriburanon; Sumit Dash; Patchara Sawakewang; Shuja Andrabi; Jon Strange; Khurram Muhammad; Chih-Ming Hung; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2025)

A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator. - Teerachot Siriburanon; Xi Chen 070; Chunxiao Liu; Jianglin Du; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2025)