A scalable network port scan detection system on FPGA. - Tejasvi Anand; Yagnesh Waghela; Kuruvilla Varghese (FPT, 2011)

A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications. - Kaushik Ghosal; Tejasvi Anand; Vikram Chaturvedi; Bharadwaj Amrutur (ICECS, 2012)

A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. - Tejasvi Anand; Mrunmay Talegaonkar; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2013)

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording. - Vikram Chaturvedi; Tejasvi Anand; Bharadwaj Amrutur (IEEE Trans. Very Large Scale Integr. Syst., 2013)

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Tejasvi Anand; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2014)

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2014)

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. - Brian Young; Karthik Reddy; Sachin Rao; Amr Elshazly; Tejasvi Anand; Pavan Kumar Hanumolu (VLSIC, 2014)

A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. - Tejasvi Anand; Amr Elshazly; Mrunmay Talegaonkar; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. - Mrunmay Talegaonkar; Amr Elshazly; Karthikeyan Reddy; Praveen Prabha; Tejasvi Anand; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2015)

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. - Ahmed Elkholy; Mrunmay Talegaonkar; Tejasvi Anand; Pavan Kumar Hanumolu (ISSCC, 2015)

A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS. - Tejasvi Anand; Kofi A. A. Makinwa; Pavan Kumar Hanumolu (VLSIC, 2015)

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Seong Joong Kim; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2015)

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. - Woo-Seok Choi; Tejasvi Anand; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. - Ahmed Elkholy; Mrunmay Talegaonkar; Tejasvi Anand; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

Toward realizing power scalable and energy proportional high-speed wireline links - Tejasvi Anand (2015)

A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity. - Tejasvi Anand; Kofi A. A. Makinwa; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (CICC, 2017)

29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS. - Ashwin Ramachandran; Arun Natarajan 001; Tejasvi Anand (ISSCC, 2017)

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump. - Soumya Bose; Tejasvi Anand; Matthew L. Johnston (CICC, 2018)

A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS. - Ashwin Ramachandran; Tejasvi Anand (ISSCC, 2018)

A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation. - Bodhisatwa Sadhu; Tejasvi Anand; Scott K. Reynolds (IEEE J. Solid State Circuits, 2018)

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. - Da Wei; Tejasvi Anand; Guanghua Shu; José E. Schutt-Ainé; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A 3.5mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting. - Soumya Bose; Tejasvi Anand; Matthew L. Johnston (CICC, 2019)

A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS. - Yusang Chun; Tejasvi Anand (CICC, 2019)

A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm. - Mohamed Megahed; Y. Ramadass; Tejasvi Anand (CICC, 2019)

A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS. - Yusang Chun; Ashwin Ramachandran; Tejasvi Anand (ESSCIRC, 2019)

A Stochastic Wireline Communication System. - Tejasvi Anand (MWSCAS, 2019)

Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator. - Soumya Bose; Tejasvi Anand; Matthew L. Johnston (IEEE J. Solid State Circuits, 2019)

A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT. - Abhishekh Devaraj; Mohamed Megahed; Yutao Liu; Ashwin Ramachandran; Tejasvi Anand (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping. - Ashwin Ramachandran; Arun Natarajan 001; Tejasvi Anand (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit. - Yusang Chun; Tejasvi Anand (IEEE J. Solid State Circuits, 2020)

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. - Ashwin Ramachandran; Yusang Chun; Mohamed Megahed; Tejasvi Anand (IEEE J. Solid State Circuits, 2020)

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (IEEE J. Solid State Circuits, 2020)

A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. - Mohamed Megahed; Yusang Chun; Zhiping Wang; Tejasvi Anand (VLSI Circuits, 2021)

A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. - Zhiping Wang; Mohamed Megahed; Yusang Chun; Tejasvi Anand (VLSI Circuits, 2021)

A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting. - Soumya Bose; Tejasvi Anand; Matthew L. Johnston (IEEE J. Solid State Circuits, 2021)

A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. - Xiaohui Lin 012; Mohamed Megahed; Tejasvi Anand (VLSI Technology and Circuits, 2022)

A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. - Yusang Chun; Mohamed Megahed; Ashwin Ramachandran; Tejasvi Anand (IEEE J. Solid State Circuits, 2022)

PLL-SAR: A New High-Speed Analog to Digital Converter Architecture. - Vladimir Veselý; Calvin Yoji Lee; Tejasvi Anand; Un-Ku Moon (MWSCAS, 2023)

A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS. - Mohamed Megahed; Tejasvi Anand (IEEE J. Solid State Circuits, 2023)

Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE). - Andrew Ensinger; Ramin Javadi; Xiaohui Lin 012; Bella Bose; Tejasvi Anand (ISCAS, 2024)

An Enhanced Eye-Opening PAM-4 with Encoding for Short-Reach Wireline Communication Systems. - Ramin Javadi; Tejasvi Anand (MWSCAS, 2024)

An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. - Mohamed Megahed; Yusang Chun; Zhiping Wang; Tejasvi Anand (IEEE J. Solid State Circuits, 2024)

A 0.055pJ/bit/dB 42Gb/s PAM-4 Wireline Transceiver with Consecutive Symbol to Center (CSC) Encoding and Classification for 26dB Loss in 16nm FinFET. - Ramin Javadi; Tejasvi Anand (CICC, 2025)