A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA. - Tengjie Sui; Zhixiang Zhao; Siwei Xie; Yangze Xie; Yanyan Zhao; Qiu Huang; Jianfeng Xu; Qiyu Peng (IEEE Trans. Instrum. Meas., 2019)

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction. - Zhipeng Song; Zhixiang Zhao; Hongsen Yu; Jingwu Yang; Xi Zhang 020; Tengjie Sui; Jianfeng Xu; Siwei Xie; Qiu Huang; Qiyu Peng (Sensors, 2020)