Reconfiguring fault-tolerant two-dimensional array architectures. - Nathaniel J. Davis IV; F. Gail Gray; Joseph A. Wegner; Shannon E. Lawson; Vinay Murthy; Tennis S. White (IEEE Micro, 1994)

PowerPC AS A10 64-bit RISC microprocessor. - James W. Bishop; Michael J. Campion; Thomas L. Jeremiah; Stephen J. Mercier; Edmond J. Mohring; Kerry P. Pfarr; Bruce G. Rudolph; Gregory S. Still; Tennis S. White (IBM J. Res. Dev., 1996)