Automatic extraction of circuit models from layout artwork for a BiCMOS technology. - Terence B. Hook (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations. - Terence B. Hook; Jay S. Burnham; Ronald J. Bolam (IBM J. Res. Dev., 1999)

Enchanced multi-threshold (MTCMOS) circuits using variable well bias. - Stephen V. Kosonocky; Michael Immediato; Peter E. Cottrell; Terence B. Hook; Randy W. Mann; Jeff Brown (ISLPED, 2001)

Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation. - Terence B. Hook; David Harmon; Chuan Lin (Microelectron. Reliab., 2001)

Ultralow-power SRAM technology. - Randy W. Mann; W. W. (Bill) Abadeer; Matthew J. Breitwisch; O. Bula; Jeff S. Brown; Bryant C. Colwill; Peter E. Cottrell; William T. Crocco Jr.; Stephen S. Furkay; Michael J. Hauser; Terence B. Hook; Dennis Hoyniak; et al. (IBM J. Res. Dev., 2003)

Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration. - Terence B. Hook; Ronald J. Bolam; William Clark; Jay S. Burnham; Nivo Rovedo; Laura Schutz (Microelectron. Reliab., 2005)

Fully depleted devices for designers: FDSOI and FinFETs. - Terence B. Hook (CICC, 2012)