Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Teresa Cervero; Sebastián López; Gustavo M. Callicó; Roberto Sarmiento (FPL, 2011)

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Roberto Sarmiento; Teresa Riesgo (ICME, 2011)

Scalable Models for Autonomous Self-Assembled Reconfigurable Systems. - Teresa Cervero; Sebastián López; Roberto Sarmiento; Tannous Frangieh; Peter Athanas (ReConFig, 2011)

A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems. - Tannous Frangieh; Richard Stroop; Peter Athanas; Teresa Cervero (ARC, 2012)

A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems. - Teresa Cervero; Julio Dondo; Ana Gomez; Xerach Peña; Sebastián López; Fernando Rincón Calle; Roberto Sarmiento; Juan Carlos López 001 (DSD, 2013)

Scalable architectures for real-time hyperspectral unmixing. - Teresa Cervero; Sebastián López; Gustavo M. Callicó; José Francisco López; Roberto Sarmiento (Microelectron. J., 2014)

A Scalable and Dynamically Reconfigurable FPGA-Based Embedded System for Real-Time Hyperspectral Unmixing. - Teresa Cervero; Julián Caba; Sebastián López; Julio Dondo; Roberto Sarmiento; Fernando Rincón; Juan Carlos López 001 (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2015)

A scalable H.264/AVC deblocking filter architecture. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Teresa Riesgo; Roberto Sarmiento (J. Real Time Image Process., 2016)

Ethernet Emulation over PCIe for RISC-V Software Development Vehicles. - David Castells-Rufas; Xavier Martorell; Aleix Roca; Alexander Kropotov; Xavier Teruel; Teresa Cervero; John D. Davis (DCIS, 2023)

b8c: SpMV accelerator implementation leveraging high memory bandwidth. - José Oliver 002; Carlos Álvarez 001; Teresa Cervero; Xavier Martorell; John D. Davis; Eduard Ayguadé (FCCM, 2023)

Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach. - José Oliver 002; Carlos Álvarez 001; Teresa Cervero; Xavier Martorell; John D. Davis; Eduard Ayguadé (FPL, 2023)

Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress. - Gopinath Mahale; Tejas Limbasiya; Muhammad Asad Aleem; Luis A. Plana; Aleksandar Duricic; Alireza Monemi; Xabier Abancens; Teresa Cervero; John D. Davis (ISC Workshops, 2023)

3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project. - Himar Fabelo; Raquel León; Emanuele Torti; Santiago Marco; Max Verbers; Yann Falevoz; Yolanda Ramallo-Fariña; Christian Weis; Ana M. Wägner; Eduardo Juárez Martínez; Claudio Rial; Alfonso Lagares; et al. (DSD, 2024)

Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs. - Elias Perdomo; Alexander Kropotov; Francelly Katherine Cano Ladino; Syed Zafar; Teresa Cervero; Xavier Martorell Bofill; Behzad Salami 001 (RAPIDO@HiPEAC, 2024)

Memory Sandbox: A Versatile Tool for Analyzing and Optimizing HBM Performance in FPGA. - Elias Perdomo; Xavier Martorell; Teresa Cervero; Behzad Salami 001 (SBAC-PAD, 2024)