Virtual registers. - Antonio González 001; Mateo Valero; José González 002; Teresa Monreal Arnal (HiPC, 1997)

Delaying Physical Register Allocation through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (MICRO, 1999)

Dynamic Register Renaming Through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (J. Instr. Level Parallelism, 2000)

Hardware Schemes for Early Register Release. - Teresa Monreal; Víctor Viñals; Antonio González 001; Mateo Valero (ICPP, 2002)

Late Allocation and Early Release of Physical Registers. - Teresa Monreal; Víctor Viñals; José González 002; Antonio González 001; Mateo Valero (IEEE Trans. Computers, 2004)

Hardware support for early register release. - Teresa Monreal; Víctor Viñals; Antonio González 001; Mateo Valero (Int. J. High Perform. Comput. Netw., 2005)

Speculative early register release. - Jesús Alastruey; Teresa Monreal; Víctor Viñals; Mateo Valero (Conf. Computing Frontiers, 2006)

Microarchitectural Support for Speculative Register Renaming. - Jesús Alastruey; Teresa Monreal; Víctor Viñals; Mateo Valero (IPDPS, 2007)

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. - Jesús Alastruey; Teresa Monreal; Francisco J. Cazorla; Víctor Viñals; Mateo Valero (SBAC-PAD, 2008)

Light NUCA: A proposal for bridging the inter-cache latency gap. - Darío Suárez Gracia; Teresa Monreal; Fernando Vallejo; Ramón Beivide; Víctor Viñals (DATE, 2009)

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. - Darío Suárez Gracia; Giorgos Dimitrakopoulos; Teresa Monreal Arnal; Manolis Katevenis; Víctor Viñals Yúfera (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. - Alexandra Ferrerón-Labari; Darío Suárez Gracia; Jesús Alastruey-Benedé; Teresa Monreal Arnal; Víctor Viñals (SBAC-PAD, 2014)

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. - Darío Suárez Gracia; Alexandra Ferrerón-Labari; Luis Montesano Del Campo; Teresa Monreal Arnal; Víctor Viñals Yúfera (ACM Trans. Archit. Code Optim., 2014)

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. - Alexandra Ferrerón-Labari; Darío Suárez Gracia; Jesús Alastruey-Benedé; Teresa Monreal Arnal; Pablo Ibáñez 001 (IEEE Trans. Computers, 2016)

Reuse Detector: Improving the Management of STT-RAM SLLCs. - Roberto Rodríguez-Rodríguez; Javier Díaz; Fernando Castro; Pablo Ibáñez 001; Daniel Chaver; Víctor Viñals; Juan Carlos Saez; Manuel Prieto-Matías; Luis Piñuel; Teresa Monreal Arnal; José María Llabería (Comput. J., 2018)

ReD: A reuse detector for content selection in exclusive shared last-level caches. - Javier Díaz; Teresa Monreal; Pablo Ibáñez 001; José M. Llabería; Víctor Viñals (J. Parallel Distributed Comput., 2019)

A fault-tolerant last level cache for CMPs operating at ultra-low voltage. - Alexandra Ferrerón-Labari; Jesús Alastruey-Benedé; Darío Suárez Gracia; Teresa Monreal Arnal; Pablo Ibáñez-Marín; Víctor Viñals Yúfera (J. Parallel Distributed Comput., 2019)

Near-optimal replacement policies for shared caches in multicore processors. - Javier Díaz; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José M. Llabería (J. Supercomput., 2021)

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. - Carlos Escuin; Asif Ali Khan; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; Jerónimo Castrillón (DroneSE/RAPIDO@HiPEAC, 2022)

Forecasting lifetime and performance of a novel NVM last-level cache with compression. - Carlos Escuin; Pablo Ibáñez 001; Teresa Monreal; José M. Llabería; Víctor Viñals (CoRR, 2022)

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. - Carlos Escuin; Pablo Ibáñez 001; Teresa Monreal; José M. Llabería; Víctor Viñals (CoRR, 2022)

Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. - Carlos Escuin; Asif Ali Khan; Pablo Ibáñez 001; Teresa Monreal; Jerónimo Castrillón; Víctor Viñals (HPCA, 2023)

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. - Carlos Escuin; Fernando García-Redondo; Mahdi Zahedi; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José María Llabería; James Myers; Julien Ryckaert; Dwaipayan Biswas; Francky Catthoor (ICECS, 2023)