A fault model for VHDL descriptions at the register transfer level. - Teresa Riesgo; Javier Uceda (EURO-DAC, 1996)

Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. - Teresa Riesgo; Yago Torroja; Eduardo de la Torre; Javier Uceda (DATE, 1998)

Design methodologies based on hardware description languages. - Teresa Riesgo; Yago Torroja; Eduardo de la Torre (IEEE Trans. Ind. Electron., 1999)

Highly Configurable Control Boards: A Tool and a Design Experience. - Eduardo de la Torre; Teresa Riesgo; Javier Uceda; E. Macip; M. Rizzi (IEEE International Workshop on Rapid System Prototyping, 2000)

Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. - Mario García-Valderas; Eduardo de la Torre; F. Ariza; Teresa Riesgo (FPL, 2004)

Flexible Core Reallocation for Virtex II Structures. - Yana Esteves Krasteva; Ana B. Jimeno; Eduardo de la Torre; Teresa Riesgo (ERSA, 2005)

Switching activity propagation of VHDL-RTL combinational designs through an automated tool. - Felipe Machado; Teresa Riesgo; Yago Torroja (ICECS, 2005)

Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. - Yana Esteves Krasteva; Ana B. Jimeno; Eduardo de la Torre; Teresa Riesgo (IEEE International Workshop on Rapid System Prototyping, 2005)

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo; Didier Joly (FPL, 2006)

Power Macromodeling for IP Modules. - Yaseer Arafat Durrani; Teresa Riesgo (ICECS, 2006)

A Hardware Library for Sensors/Actuators Interfaces in Sensor Networks. - Jorge Portilla; José Luis Buron; Teresa Riesgo; Angel de Castro (ICECS, 2006)

Power estimation for register transfer level by genetic algorithm. - Yaseer Arafat Durrani; Teresa Riesgo; Felipe Machado (ICINCO-RA, 2006)

Power Estimation for IP-Based Modules. - Yaseer Arafat Durrani; Teresa Riesgo (SoC, 2006)

A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. - Felipe Machado; Teresa Riesgo; Yago Torroja (PATMOS, 2006)

Power Macromodeling for High Level Power Estimation. - Yaseer Arafat Durrani; Teresa Riesgo (ReCoSoC, 2006)

Partial Reconfiguration for Core Reallocation and Flexible Communications. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2006)

Ubiquitous Computing and Ambient Intelligence: New Challenges for Computing. - José Bravo 001; Xavier Alamán; Teresa Riesgo (J. Univers. Comput. Sci., 2006)

A Modular Architecture for Nodes in Wireless Sensor Networks. - Jorge Portilla; Angel de Castro; Eduardo de la Torre; Teresa Riesgo (J. Univers. Comput. Sci., 2006)

LUT-Based Power Macromodeling Technique for DSP Architectures. - Yaseer Arafat Durrani; Teresa Riesgo (ICECS, 2007)

Efficient Power Macromodeling Technique for IP-Based Digital System. - Yaseer Arafat Durrani; Ana Abril; Teresa Riesgo (ISCAS, 2007)

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ISCAS, 2007)

A digital system to emulate wireless networks. - Eduardo Peña; Eduardo de la Torre; Angel de Castro; Teresa Riesgo (IET Comput. Digit. Tech., 2007)

Architectural Power Analysis for Intellectual Property-Based Digital System. - Yaseer Arafat Durrani; Teresa Riesgo (J. Low Power Electron., 2007)

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. - Felipe Machado; Teresa Riesgo; Yago Torroja (PATMOS, 2008)

A Fast Emulation-Based NoC Prototyping Framework. - Yana Esteves Krasteva; Francisco Criado; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2008)

A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation. - Felipe Machado; Yago Torroja; Teresa Riesgo (J. Low Power Electron., 2008)

A Piezoelectric Minirheometer for Measuring the Viscosity of Polymer Microsamples. - Almudena M. Sánchez; Roberto Prieto; Manuel Laso; Teresa Riesgo (IEEE Trans. Ind. Electron., 2008)

Power estimation technique for DSP architectures. - Yaseer Arafat Durrani; Teresa Riesgo (Digit. Signal Process., 2009)

Reconfigurable Hardware Architecture of a Shape Recognition System Based on Specialized Tiny Neural Networks With Online Training. - Félix Moreno; Jaime Alarcón; Rubén Salvador; Teresa Riesgo (IEEE Trans. Ind. Electron., 2009)

Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. - Rubén Salvador; Félix Moreno; Teresa Riesgo; Lukás Sekanina (AHS, 2010)

Generic Systolic Array for Run-Time Scalable Cores. - Andrés Otero; Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ARC, 2010)

A Modular Peripheral to Support Self-Reconfiguration in SoCs. - Andrés Otero; Angel Morales-Cas; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (DSD, 2010)

High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. - Rubén Salvador; Félix Moreno; Teresa Riesgo; Lukás Sekanina (DSD, 2010)

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Yana Esteves Krasteva (FPL, 2010)

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. - Jorge Portilla; Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Oliver Stecklina; Steffen Peter; Peter Langendörfer (Int. J. Distributed Sens. Networks, 2010)

Reconfigurable Networks on Chip: DRNoC architecture. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (J. Syst. Archit., 2010)

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. - Andrés Otero; Rubén Salvador; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Teresa Cervero; Sebastián López; Gustavo M. Callicó; Roberto Sarmiento (FPL, 2011)

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Roberto Sarmiento; Teresa Riesgo (ICME, 2011)

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. - Wei He 015; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2011)

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Lukás Sekanina; Teresa Riesgo (ReConFig, 2011)

Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. - Rubén Salvador; Félix Moreno; Teresa Riesgo; Lukás Sekanina (EURASIP J. Adv. Signal Process., 2011)

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. - Wei He 015; Eduardo de la Torre; Teresa Riesgo (COSADE, 2012)

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (FPL, 2012)

Low-complexity timing synchronization scheme for MB-OFDM UWB receiver based on sign-bit. - Guixuan Liang; Jorge Portilla; Teresa Riesgo (ICUWB, 2012)

Simulation tool and case study for planning wireless sensor network. - Danping He; Gabriel Mujica; Jorge Portilla; Teresa Riesgo (IECON, 2012)

Hardware-software integration platform for a WSN testbed based on cookies nodes. - Gabriel Mujica; Victor Rosello; Jorge Portilla; Teresa Riesgo (IECON, 2012)

Smart parking service based on Wireless Sensor Networks. - Jihoon Yang; Jorge Portilla; Teresa Riesgo (IECON, 2012)

Automatic generation of identical routing pairs for FPGA implemented DPL logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Power management techniques in an FPGA-based WSN node for high performance applications. - Miguel Lombardo; Julio Camarero; Juan Valverde; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2012)

A hardware in the loop design methodology for FPGA system and its application to complex functions. - Guixuan Liang; Danping He; Jorge Portilla; Teresa Riesgo (VLSI-DAT, 2012)

Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory. - Juan Valverde; Victor Rosello; Gabriel Mujica; Jorge Portilla; Amaia Uriarte; Teresa Riesgo (Int. J. Distributed Sens. Networks, 2012)

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. - Rubén Salvador; Alberto Vidal; Félix Moreno; Teresa Riesgo; Lukás Sekanina (Microprocess. Microsystems, 2012)

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. - Juan Valverde; Andrés Otero; Miguel Lopez; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (Sensors, 2012)

A noise-agnostic self-adaptive image processing application based on evolvable hardware. - Javier Mora 001; Angel Gallego; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. - Javier Mora 001; Angel Gallego; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

A self-adaptive image processing application based on evolvable and scalable hardware. - Angel Gallego; Javier Mora 001; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (FPL, 2013)

A 3D multi-objective optimization planning algorithm for wireless sensor networks. - Danping He; Jorge Portilla; Teresa Riesgo (IECON, 2013)

On-the-fly dynamic reprogramming mechanism for increasing the energy efficiency and supporting multi-experimental capabilities in WSNs. - Gabriel Mujica; Victor Rosello; Jorge Portilla; Teresa Riesgo (IECON, 2013)

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. - Angel Gallego; Javier Mora 001; Andrés Otero; Rubén Salvador; Eduardo de la Torre; Teresa Riesgo (IPDPS Workshops, 2013)

A scalable evolvable hardware processing array. - Angel Gallego; Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2013)

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (IEEE Trans. Computers, 2013)

Power-aware multi-objective evolvable hardware system on an FPGA. - Blanca López; Juan Valverde; Eduardo de la Torre; Teresa Riesgo (AHS, 2014)

A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. - Filip Veljkovic; Teresa Riesgo; Eduardo de la Torre; Raul Regada; Luis Berrojo (AHS, 2014)

A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. - Juan Valverde; Alfonso Rodríguez 002; Julio Camarero; Andrés Otero; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (FPL, 2014)

Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. - Alfonso Rodríguez 002; Juan Valverde; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2014)

High-Level Power Analysis for Intellectual Property-Based Digital Systems. - Yaseer Arafat Durrani; Teresa Riesgo (Circuits Syst. Signal Process., 2014)

Power estimation for intellectual property-based digital systems at the architectural level. - Yaseer Arafat Durrani; Teresa Riesgo (J. King Saud Univ. Comput. Inf. Sci., 2014)

Radio propagation modeling and real test of ZigBee based indoor wireless sensor networks. - Danping He; Gabriel Mujica; Guixuan Liang; Jorge Portilla; Teresa Riesgo (J. Syst. Archit., 2014)

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (Microprocess. Microsystems, 2014)

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. - Filip Veljkovic; Teresa Riesgo; Eduardo de la Torre (AHS, 2015)

A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems. - Gabriel Mujica; Alejandro Garcia; Javier Gordillo; Jorge Portilla; Teresa Riesgo (ISCAS, 2015)

Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. - Alfonso Rodríguez 002; Juan Valverde; Cesar Castanares; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (ISCAS, 2015)

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. - Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2015)

Execution modeling in self-aware FPGA-based architectures for efficient resource management. - Alfonso Rodríguez 002; Juan Valverde; Cesar Castanares; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2015)

Modelling and planning reliable wireless sensor networks based on multi-objective optimization genetic algorithm with changeable length. - Danping He; Gabriel Mujica; Jorge Portilla; Teresa Riesgo (J. Heuristics, 2015)

Multiple feature points representation in target localization of wireless visual sensor networks. - Wei Li 206; Jorge Portilla; Félix Moreno; Guixuan Liang; Teresa Riesgo (J. Netw. Comput. Appl., 2015)

Performance evaluation of an AODV-based routing protocol implementation by using a novel in-field WSN diagnosis tool. - Gabriel Mujica; Jorge Portilla; Teresa Riesgo (Microprocess. Microsystems, 2015)

Letter from the guest editors of the special issue on DCIS 2014. - Eduardo de la Torre; Jorge Portilla; Teresa Riesgo (Microprocess. Microsystems, 2015)

A scalable H.264/AVC deblocking filter architecture. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Teresa Riesgo; Roberto Sarmiento (J. Real Time Image Process., 2016)

Efficient power analysis approach and its application to system-on-chip design. - Yaseer Arafat Durrani; Teresa Riesgo (Microprocess. Microsystems, 2016)

Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project. - Christos P. Antonopoulos; Katerina Asimogloy; Sarah Chiti; Luca D'Onofrio; Simone Gianfranceschi; Danping He; Antonio Iodice; Stavros A. Koubias; Christos Koulamas; Luciano Lavagno; Mihai T. Lazarescu; Gabriel Mujica; et al. (Sensors, 2016)

Embedded Emotion Recognition within Cyber-Physical Systems using Physiological Signals. - Jose Angel Miranda Calero; Rodrigo Marino; José Manuel Lanza-Gutiérrez; Teresa Riesgo; Mario García-Valderas; Celia López-Ongil (DCIS, 2018)

Poster: Smart Self-Adaptive Clustering Technique for Collaborative Sensing in IoT Risk Contexts. - Jaime Zornoza; Gabriel Mujica; Jorge Portilla; Teresa Riesgo (EWSN, 2018)

Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs. - Rodrigo Marino; José Manuel Lanza-Gutiérrez; Teresa Riesgo; Miguel Holgado (ISCAS, 2018)

Edge and Fog Computing Platform for Data Fusion of Complex Heterogeneous Sensors. - Gabriel Mujica; Roberto Rodriguez-Zurrunero; Mark Richard Wilby; Jorge Portilla; Ana Belén Rodríguez-González; Álvaro Araujo; Teresa Riesgo; Juan José Vinagre-Díaz (Sensors, 2018)

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. - Alfonso Rodríguez 002; Juan Valverde; Jorge Portilla; Andrés Otero; Teresa Riesgo; Eduardo de la Torre (Sensors, 2018)

Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. - Rodrigo Marino; Sergio Quintero; José Manuel Lanza-Gutiérrez; Teresa Riesgo; Miguel Holgado; Jorge Portilla; Eduardo de la Torre (DCIS, 2019)

A Novel Data Processing Technique for Expert Resonant Nano-Pillars Transducers: A Case Study Measuring Ethanol in Water and Wine Liquid Matrices. - Sergio Quintero; Rodrigo Marino; José Manuel Lanza-Gutiérrez; Francisco Javier Sanza; Teresa Riesgo; Miguel Holgado (IEEE Access, 2019)

Towards an Machine Learning-Based Edge Computing Oriented Monitoring System for the Desert Border Surveillance Use Case. - Khalifa M. Bellazi; Rodrigo Marino; José Manuel Lanza-Gutiérrez; Teresa Riesgo (IEEE Access, 2020)