On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. - Kai-Pui Lam; Sui-Tung Mak (FPL, 2002)

Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing. - Sui-Tung Mak; Kai-Pui Lam (FPT, 2002)

High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. - Terrence S. T. Mak; Kai-Pui Lam (CSB, 2003)

An FPGA-based eigenfilter using fast Hebbian learning. - Kai-Pui Lam; Sui-Tung Mak (ICASSP (2), 2003)

Field programmable gate arrays and analog implementation of BRIN for optimization problems. - H. S. Ng; Sui-Tung Mak; Kai-Pui Lam (ISCAS (5), 2003)

Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. - Terrence S. T. Mak; Kai-Pui Lam (CSB, 2004)

FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. - Terrence S. T. Mak; Kai-Pui Lam (FPL, 2004)

On Computing Maximum Likelihood Phylogeny Using FPGA p. - Terrence S. T. Mak; Kai-Pui Lam (FPL, 2004)

On-FPGA Communication Architectures and Design Factors. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPL, 2006)

A Current-Mode Analog Circuit for Reinforcement Learning Problems. - Terrence S. T. Mak; Kai-Pui Lam; H. S. Ng; Guy Rachmuth; Chi-Sang Poon (ISCAS, 2007)

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (NOCS, 2007)

High-throughput interconnect wave-pipelining for global communication in FPGAs. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPGA, 2008)

Wave-pipelined signaling for on-FPGA communication. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPT, 2008)

Implementation of Wave-Pipelined Interconnects in FPGAs. - Terrence S. T. Mak; Crescenzo D'Alessandro; N. Pete Sedcole; Peter Y. K. Cheung; Alexandre Yakovlev; Wayne Luk (NOCS, 2008)

Global interconnections in FPGAs: modeling and performance analysis. - Terrence S. T. Mak; Crescenzo D'Alessandro; N. Pete Sedcole; Peter Y. K. Cheung; Alexandre Yakovlev; Wayne Luk (SLIP, 2008)

Interconnection lengths and delays estimation for communication links in FPGAs. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (SLIP, 2008)

A DP-network for optimal dynamic routing in network-on-chip. - Terrence S. T. Mak; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (CODES+ISSS, 2009)

Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. - Li Wang; Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung (ISCAS, 2009)

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. - Bo Yu 014; Terrence S. T. Mak; Xiangyu Li; Fei Xia 001; Alexandre Yakovlev; Yihe Sun; Chi-Sang Poon (FPL, 2010)

Wave-pipelined intra-chip signaling for on-FPGA communications. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (Integr., 2010)

A CMOS Current-Mode Dynamic Programming Circuit. - Terrence S. T. Mak; Kai-Pui Lam; H. S. Ng; Guy Rachmuth; Chi-Sang Poon (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems. - Yu Zhou 006; Terrence S. T. Mak; Alex Yakovlev (ACSD, 2011)

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Fei Xia 001; Alexandre Yakovlev; Maurizio Palesi (DATE, 2011)

Redressing timing issues for speed-independent circuits in deep submicron age. - Yu Li; Terrence S. T. Mak; Alex Yakovlev (DATE, 2011)

Feasibility study for future implantable neural-silicon interface devices. - Allann Al-armaghany; Bo Yu 014; Terrence S. T. Mak; Kin-Fai Tong; Yihe Sun (EMBC, 2011)

Towards neuro-silicon interface using reconfigurable dynamic clamping. - Junwen Luo; Terrence S. T. Mak; Bo Yu 014; Peter Andras 001; Alex Yakovlev (EMBC, 2011)

Real-time neuronal networks reconstruction using hierarchical systolic arrays. - Bo Yu 014; Terrence S. T. Mak; Yihe Sun; Chi-Sang Poon (EMBC, 2011)

Memory efficient on-line streaming for multichannel spike train analysis. - Bo Yu 014; Terrence S. T. Mak; Leslie Smith; Yihe Sun; Alex Yakovlev; Chi-Sang Poon (EMBC, 2011)

On-chip dynamic programming networks using 3D-TSV integration. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Kuan Zhou; Kai-Pui Lam; Yicong Meng; Alexandre Yakovlev; Chi-Sang Poon (ICSAMOS, 2011)

Power adaptive computing system design in energy harvesting environment. - Qiang Liu 011; Terrence S. T. Mak; Junwen Luo; Wayne Luk; Alexandre Yakovlev (ICSAMOS, 2011)

Communication centric on-chip power grid models for networks-on-chip. - Nizar Dahir; Terrence S. T. Mak; Alex Yakovlev (VLSI-SoC, 2011)

Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. - Kai-Pui Lam; Terrence S. T. Mak; Chi-Sang Poon (VLSI-SoC, 2011)

Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. - Kai-Pui Lam; Terrence S. T. Mak; Chi-Sang Poon (VLSI-SoC, 2011)

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters. - Bo Yu 014; Terrence S. T. Mak; Xiangyu Li; Fei Xia 001; Alexandre Yakovlev; Yihe Sun; Chi-Sang Poon (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. - Terrence S. T. Mak; Peter Y. K. Cheung; Kai-Pui Lam; Wayne Luk (IEEE Trans. Ind. Electron., 2011)

Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication. - Andrew Mundy; Terrence S. T. Mak; Alex Yakovlev; Simon Davidson; Steve B. Furber (ACSD, 2012)

Minimizing power supply noise through harmonic mappings in networks-on-chip. - Nizar Dahir; Terrence S. T. Mak; Fei Xia 001; Alex Yakovlev (CODES+ISSS, 2012)

A scalable FPGA-based design for field programmable large-scale ion channel simulations. - Graeme Coapes; Terrence S. T. Mak; Junwen Luo; Alex Yakovlev; Chi-Sang Poon (FPL, 2012)

Intra-chip physical parameter sensor for FPGAS using flip-flop metastability. - Ghaith Tarawneh; Terrence S. T. Mak; Alex Yakovlev (FPL, 2012)

Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip. - Nizar Dahir; Ra'ed Al-Dujaily; Alex Yakovlev; Petros Missailidis; Terrence S. T. Mak (NoCArc@MICRO, 2012)

Surface wave communication system for on-chip and off-chip interconnects. - Ammar Karkar; Ra'ed Al-Dujaily; Alex Yakovlev; Kenneth Tong; Terrence S. T. Mak (NoCArc@MICRO, 2012)

Truncation error analysis of MTBF computation for multi-latch synchronizers. - Terrence S. T. Mak (Microelectron. J., 2012)

Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Fei Xia 001; Alex Yakovlev; Maurizio Palesi (IEEE Trans. Parallel Distributed Syst., 2012)

Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms. - Athanasios K. Grivas; Terrence S. T. Mak; Alex Yakovlev; Jonny Wray (ASAP, 2013)

A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers. - Junshi Wang; Xiaohang Wang 001; Letian Huang; Terrence S. T. Mak; Guangjun Li (DASC, 2013)

A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era. - Xiaohang Wang 001; Zhiming Li; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab; Terrence S. T. Mak (ESTIMedia, 2013)

Towards reliable hybrid bio-silicon integration using novel adaptive control system. - Junwen Luo; Patrick Degenaar; Graeme Coapes; Alex Yakovlev; Terrence S. T. Mak; Peter Andras 001 (ISCAS, 2013)

On multicast for dynamic and irregular on-chip networks using dynamic programming method. - Wen Zong; Xiaohang Wang 001; Terrence S. T. Mak (NoCArc@MICRO, 2013)

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. - Xiaohang Wang 001; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab; Maurizio Palesi (NOCS, 2013)

Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Kai-Pui Lam; Fei Xia 001; Alex Yakovlev; Chi-Sang Poon (Comput. J., 2013)

Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip. - Nizar Dahir; Terrence S. T. Mak; Ra'ed Al-Dujaily; Alex Yakovlev (IET Comput. Digit. Tech., 2013)

Hybrid wire-surface wave interconnects for next-generation networks-on-chip. - Ammar Karkar; Janice E. Turner; Kenneth Tong; Ra'ed Al-Dujaily; Terrence S. T. Mak; Alex Yakovlev; Fei Xia 001 (IET Comput. Digit. Tech., 2013)

Efficient multicast schemes for 3-D Networks-on-Chip. - Xiaohang Wang 001; Mei Yang 001; Yingtao Jiang; Maurizio Palesi; Peng Liu 016; Terrence S. T. Mak; Nader Bagherzadeh (J. Syst. Archit., 2013)

On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network. - Bo Yu 014; Rosa H. M. Chan; Terrence S. T. Mak; Yihe Sun; Chi-Sang Poon (IEEE Trans. Biomed. Eng., 2013)

Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems. - Ra'ed Al-Dujaily; Nizar Dahir; Terrence S. T. Mak; Fei Xia 001; Alex Yakovlev (ACM Trans. Design Autom. Electr. Syst., 2013)

Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources. - Xiaohang Wang 001; Zhiming Li; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab; Terrence S. T. Mak (ASP-DAC, 2014)

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip. - Ammar Karkar; Nizar Dahir; Ra'ed Al-Dujaily; Kenneth Tong; Terrence S. T. Mak; Alex Yakovlev (DATE, 2014)

Adaptive power allocation for many-core systems inspired from multiagent auction model. - Xiaohang Wang 001; Baoxin Zhao; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab; Maurizio Palesi (DATE, 2014)

A scalable FPGA-based cerebellum for passage-of-time representation. - Junwen Luo; Graeme Coapes; Terrence S. T. Mak; Tadashi Yamazaki; Chung Tin; Patrick Degenaar (EMBC, 2014)

A real-time silicon cerebellum spiking neural model based on FPGA. - Junwen Luo; Graeme Coapes; Patrick Degenaar; Tadashi Yamazaki; Terrence S. T. Mak; Chung Tin (ISIC, 2014)

Intra- and inter-chip voltage droop analysis using a power delivery grid model. - Wing Oi Siu; Terrence S. T. Mak (ISIC, 2014)

A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI. - Jim Ng; Terrence S. T. Mak (NoCArc@MICRO, 2014)

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip. - Nizar Dahir; Ghaith Tarawneh; Terrence S. T. Mak; Ra'ed Al-Dujaily; Alex Yakovlev (PDP, 2014)

Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip. - Liang Wang 020; Xiaohang Wang 001; Terrence S. T. Mak (VLSI-SoC, 2014)

Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip. - Liang Wang 020; Xiaohang Wang 001; Terrence S. T. Mak (VLSI-SoC (Selected Papers), 2014)

Introduction to the Special Issue on Network-on-Chip Architectures. - Masoud Daneshtalab; Maurizio Palesi; Terrence S. T. Mak (Comput. Electr. Eng., 2014)

Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip. - Nizar Dahir; Terrence S. T. Mak; Fei Xia 001; Alexandre Yakovlev (IEEE Trans. Computers, 2014)

Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks. - Nizar Dahir; Ra'ed Al-Dujaily; Terrence S. T. Mak; Alex Yakovlev (ACM Trans. Embed. Comput. Syst., 2014)

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. - Xiaohang Wang 001; Mei Yang 001; Yingtao Jiang; Peng Liu 016; Masoud Daneshtalab; Maurizio Palesi; Terrence S. T. Mak (ACM Trans. Embed. Comput. Syst., 2014)

Eliminating Synchronization Latency Using Sequenced Latching. - Ghaith Tarawneh; Alex Yakovlev; Terrence S. T. Mak (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fine-grained runtime power budgeting for networks-on-chip. - Xiaohang Wang 001; Tengfei Wang; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab (ASP-DAC, 2015)

Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting. - Ammar Karkar; Kin-Fai Tong; Terrence S. T. Mak; Alexandre Yakovlev (DATE, 2015)

Towards reliability and performance-aware Wireless Network-on-Chip design. - Michael Opoku Agyeman; Kin-Fai Tong; Terrence S. T. Mak (DFTS, 2015)

An Improved Wireless Communication Fabric for Emerging Network-on-Chip Design. - Michael Opoku Agyeman; Kenneth Tong; Terrence S. T. Mak (FNC/MobiSPC, 2015)

On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures. - Michael Opoku Agyeman; Ji-Xiang Wan; Quoc-Tuan Vien; Wen Zong; Alex Yakovlev; Kenneth Tong; Terrence S. T. Mak (MCSoC, 2015)

Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design. - Michael Opoku Agyeman; Wen Zong; Ji-Xiang Wan; Alex Yakovlev; Kenneth Tong; Terrence S. T. Mak (NOCS, 2015)

Unbiased Regional Congestion Aware Selection Function for NoCs. - Wen Zong; Michael Opoku Agyeman; Xiaohang Wang 001; Terrence S. T. Mak (NOCS, 2015)

DeFrag: Defragmentation for Efficient Runtime Resource Allocation in NoC-Based Many-core Systems. - Jim Ng; Xiaohang Wang 001; Amit Kumar Singh 002; Terrence S. T. Mak (PDP, 2015)

Introduction to the special issue on NoC-based many-core architectures. - Masoud Daneshtalab; Maurizio Palesi; Terrence S. T. Mak (Comput. Electr. Eng., 2015)

An efficient runtime power allocation scheme for many-core systems inspired from auction theory. - Xiaohang Wang 001; Baoxin Zhao; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab (Integr., 2015)

A Survey of Wireless Sensor Network Based Air Pollution Monitoring Systems. - Wei Ying Yi; Kin Ming Lo; Terrence S. T. Mak; Kwong-Sak Leung; Yee Leung; Helen Mei-Ling Meng (Sensors, 2015)

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems. - Qiang Liu 011; Terrence S. T. Mak; Tao Zhang 025; Xinyu Niu; Wayne Luk; Alex Yakovlev (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Analytical Channel Model for Emerging Wireless Networks-on-Chip. - Michael Opoku Agyeman; Quoc-Tuan Vien; Terrence S. T. Mak (CSE/EUC/DCABES, 2016)

Modular sensor system (MSS) for urban air pollution monitoring. - Wei-Ying Yi; Kwong-Sak Leung; Yee Leung; Helen Mei-Ling Meng; Terrence S. T. Mak (IEEE SENSORS, 2016)

An Efficient Channel Model for Evaluating Wireless NoC Architectures. - Michael Opoku Agyeman; Quoc-Tuan Vien; Gary Hill; Scott J. Turner; Terrence S. T. Mak (SBAC-PAD (Workshops), 2016)

A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. - Ra'ed Al-Dujaily; An Li; Robert G. Maunder; Terrence S. T. Mak; Bashir M. Al-Hashimi; Lajos Hanzo (IEEE Access, 2016)

On runtime adaptive tile defragmentation for resource management in many-core systems. - Xiaohang Wang 001; Ting Fei; Boquan Zhang; Terrence S. T. Mak (Microprocess. Microsystems, 2016)

A pareto-optimal runtime power budgeting scheme for many-core systems. - Xiaohang Wang 001; Baoxin Zhao; Ling Wang 005; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab (Microprocess. Microsystems, 2016)

Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System. - Junwen Luo; Graeme Coapes; Terrence S. T. Mak; Tadashi Yamazaki; Chung Tin; Patrick Degenaar (IEEE Trans. Biomed. Circuits Syst., 2016)

Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip. - Liang Wang 020; Xiaohang Wang 001; Terrence S. T. Mak (IEEE Trans. Computers, 2016)

On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems. - Xiaohang Wang 001; Baoxin Zhao; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab (IEEE Trans. Computers, 2016)

IP Protection of Mesh NoCs Using Square Spiral Routing. - Qiang Liu 011; Wenqing Ji; Qi Chen; Terrence S. T. Mak (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems. - Jim Ng; Xiaohang Wang 001; Amit Kumar Singh 002; Terrence S. T. Mak (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Runtime task mapping for lifetime budgeting in many-core systems. - Liang Wang 020; Xiaohang Wang 001; Ho-fung Leung; Terrence S. T. Mak (FDL, 2017)

Throughput Optimization for Lifetime Budgeting in Many-Core Systems. - Liang Wang 020; Xiaohang Wang 001; Ho-fung Leung; Terrence S. T. Mak (ACM Great Lakes Symposium on VLSI, 2017)

On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC. - Bing Li; Xiaohang Wang 001; Amit Kumar Singh 002; Terrence S. T. Mak (NOCS, 2017)

On the Nanocommunications at THz Band in Graphene-Enabled Wireless Network-on-Chip. - Quoc-Tuan Vien; Michael Opoku Agyeman; Tuan Anh Le 002; Terrence S. T. Mak (CoRR, 2017)

HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management. - Xiaohang Wang 001; Yingtao Jiang; Mei Yang 001; Hong Li; Terrence S. T. Mak (IEEE Trans. Computers, 2017)

A Resilient 2-D Waveguide Communication Fabric for Hybrid Wired-Wireless NoC Design. - Michael Opoku Agyeman; Quoc-Tuan Vien; Ali Ahmadinia; Alexandre Yakovlev; Kin-Fai Tong; Terrence S. T. Mak (IEEE Trans. Parallel Distributed Syst., 2017)

A high-speed design methodology for inductive coupling links in 3D-ICs. - Benjamin J. Fletcher; Shidhartha Das; Terrence S. T. Mak (DATE, 2018)

Low-power 3D integration using inductive coupling links for neurotechnology applications. - Benjamin J. Fletcher; Shidhartha Das; Chi-Sang Poon; Terrence S. T. Mak (DATE, 2018)

Improving the efficiency of thermal covert channels in multi-/many-core systems. - Zijun Long; Xiaohang Wang 001; Yingtao Jiang; Guofeng Cui; Li Zhang; Terrence S. T. Mak (DATE, 2018)

Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems. - Qian Ding; Benjamin J. Fletcher; Terrence S. T. Mak (ISCAS, 2018)

On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems. - Yiming Zhao; Xiaohang Wang 001; Yingtao Jiang; Mei Yang 001; Amit Kumar Singh 002; Terrence S. T. Mak (SoCC, 2018)

Special session on bringing cores closer together: The wireless revolution in on-chip communication. - Terrence S. T. Mak; Hiroki Matsutani; Partha Pratim Pande (VTS, 2018)

An integrated web-based air pollution decision support system - a prototype. - Yee Leung; Kwong-Sak Leung; Man Hon Wong 001; Terrence S. T. Mak; Kwan-Yau Cheung; Leung-Yau Lo; Wei Ying Yi; Yuan-Lin Dong (Int. J. Geogr. Inf. Sci., 2018)

A Genetic Algorithm with New Local Operators for Multiple Traveling Salesman Problems. - Kin Ming Lo; Wei Ying Yi; Pak-Kan Wong; Kwong-Sak Leung; Yee Leung; Sui-Tung Mak (Int. J. Comput. Intell. Syst., 2018)

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip. - Ling Wang 005; Terrence S. T. Mak (J. Circuits Syst. Comput., 2018)

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip. - Li Zhang; Xiaohang Wang 001; Yingtao Jiang; Mei Yang 001; Terrence S. T. Mak; Amit Kumar Singh 002 (J. Syst. Archit., 2018)

A neuro-inspired visual tracking method based on programmable system-on-chip platform. - Shufan Yang; KongFatt Wong-Lin; James Andrew; Terrence S. T. Mak; T. Martin McGinnity (Neural Comput. Appl., 2018)

Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems. - Xiaohang Wang 001; Amit Kumar Singh 002; Bing Li; Yang Yang; Hong Li; Terrence S. T. Mak (IEEE Trans. Computers, 2018)

Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects. - Ammar Karkar; Terrence S. T. Mak; Nizar Dahir; Ra'ed Al-Dujaily; Kin-Fai Tong; Alex Yakovlev (IEEE Trans. Emerg. Top. Comput., 2018)

CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs. - Benjamin J. Fletcher; Shidhartha Das; Terrence S. T. Mak (DATE, 2019)

ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. - Siyuan Xiao; Xiaohang Wang 001; Maurizio Palesi; Amit Kumar Singh 002; Terrence S. T. Mak (DATE, 2019)

A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration. - Benjamin J. Fletcher; Terrence S. T. Mak; Shidhartha Das (ESSCIRC, 2019)

Type-Spread Molecular Communications: Principles and Inter-Symbol Interference Mitigation. - Weidong Gao 004; Terrence S. T. Mak; Lie-Liang Yang (ICC, 2019)

A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration. - Benjamin J. Fletcher; Shidhartha Das; Terrence S. T. Mak (ISLPED, 2019)

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. - Liang Wang 020; Ping Lv; Leibo Liu; Jie Han 001; Ho-fung Leung; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei; Terrence S. T. Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs. - Liang Wang 020; Xiaohang Wang 001; Ho-fung Leung; Terrence S. T. Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

On Runtime Communication and Thermal-Aware Application Mapping and Defragmentation in 3D NoC Systems. - Bing Li; Xiaohang Wang 001; Amit Kumar Singh 002; Terrence S. T. Mak (IEEE Trans. Parallel Distributed Syst., 2019)

Design and Optimization of Inductive-Coupling Links for 3-D-ICs. - Benjamin J. Fletcher; Shidhartha Das; Terrence S. T. Mak (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 Simultaneous Wireless Inter-Tier Data and Power Transfer. - Benjamin J. Fletcher; Terrence S. T. Mak; Shidhartha Das (VLSI Circuits, 2020)

On hardware-trojan-assisted power budgeting system attack targeting many core systems. - Yiming Zhao; Xiaohang Wang 001; Yingtao Jiang; Liang Wang 020; Mei Yang 001; Amit Kumar Singh 002; Terrence S. T. Mak (J. Syst. Archit., 2020)

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration. - Benjamin J. Fletcher; Shidhartha Das; Terrence S. T. Mak (IEEE J. Solid State Circuits, 2020)

A Fast-Transient Response Digital Low-Dropout Regulator With Dual-Modes Tuning Technique. - Libo Qian; Da Li; Kefang Qian; Yidie Ye; Yinshui Xia; Terrence S. T. Mak (IEEE Trans. Circuits Syst., 2020)

An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems. - Qian Ding; Graham Knight; Terrence S. T. Mak (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective. - Weilong Chen; Xiaohang Wang 001; Ye Sun; Qiao Hu; Letian Huang; Yingtao Jiang; Amit Kumar Singh 002; Terrence S. T. Mak; Mei Yang 001 (IEEE Access, 2021)

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. - Nizar Dahir; Ammar Karkar; Maurizio Palesi; Terrence S. T. Mak; Alex Yakovlev (Integr., 2021)

On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. - Siyuan Xiao; Xiaohang Wang 001; Maurizio Palesi; Amit Kumar Singh 002; Liang Wang 020; Terrence S. T. Mak (IEEE Trans. Computers, 2021)

Molecular Type Spread Molecular Shift Keying for Multiple-Access Diffusive Molecular Communications. - Weidong Gao 004; Terrence S. T. Mak; Lie-Liang Yang (IEEE Trans. Mol. Biol. Multi Scale Commun., 2021)

Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era. - Ammar Karkar; Nizar Dahir; Terrence S. T. Mak; Kin-Fai Tong (ACM J. Emerg. Technol. Comput. Syst., 2022)