Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. - Valavan Manohararajah; Terry P. Borer; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2002)

Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. - Deshanand P. Singh; Terry P. Borer; Stephen Dean Brown (VLSI, 2003)

The Quartus University Interface Program: enabling advanced FPGA research. - Shawn Malhotra; Terry P. Borer; Deshanand P. Singh; Stephen Dean Brown (FPT, 2004)

Modular Partitioning for Incremental Compilation. - Mehrdad Eslami Dehkordi; Stephen Dean Brown; Terry P. Borer (FPL, 2006)