Neural network simulator for spatiotemporal pattern analysis. - Atsushi Kamo; Hiroshi Ninomiya; Teru Yoneyama; Hideki Asai (ICECS, 1998)

Design method of neural networks for limit cycle generator. - Teru Yoneyama; Hiroshi Ninomiya; Hideki Asai (IJCNN, 1999)

Design Method of Limit Cycle Generator by Hysteresis Neural Networks. - Teru Yoneyama; Hideki Asai; Hiroshi Ninomiya (IJCNN (3), 2000)

Two floating resistor circuits and their applications to synaptic weights in analog neural networks. - Shashidhar Tantry; Teru Yoneyama; Hideki Asai (ISCAS (1), 2001)

A low voltage floating resistor having positive and negative resistance values. - Shashidhar Tantry; Takao Oura; Teru Yoneyama; Hideki Asai (APCCAS (1), 2002)

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. - Takao Oura; Teru Yoneyama; Shashidhar Tantry; Hideki Asai (ISCAS (3), 2002)

A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values. - Takao Oura; Teru Yoneyama; Shashidhar Tantry; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally. - Tsutomu Suzuki; Takao Oura; Teru Yoneyama; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values. - Shashidhar Tantry; Yasuyuki Hiraku; Takao Oura; Teru Yoneyama; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)