Syndrome-Testable Design of Programmable Logic Arrays. - Teruhiko Yamada (ITC, 1983)

Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". - Teruhiko Yamada; Takashi Nanya (IEEE Trans. Computers, 1983)

Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. - Teruhiko Yamada; Takashi Nanya (IEEE Trans. Computers, 1984)

PLAYER: a PLA design system for VLSI's. - Yoshiyuki Koseki; Teruhiko Yamada (DAC, 1985)

Syndrome-testable design and syndrome computing method for large PLA's. - Teruhiko Yamada (Syst. Comput. Jpn., 1986)

Test research in Japan. - Hideo Fujiwara; Yuzo Takamatsu; Takashi Nanya; Teruhiko Yamada; Hideo Tamamoto; Kiyoshi Furuya (IEEE Des. Test, 1988)

Pseudorandom pattern built-in self-test for embedded rams. - Teruhiko Yamada; Hiroshi Nakajima (Syst. Comput. Jpn., 1990)

Method of diagnosing multiple stuck-at-faults in combinational circuits. - Teruhiko Yamada; Shuji Hamada; Tatsuo Matsumoto; Toshihiko Takahashi; Takao Nakayama (Syst. Comput. Jpn., 1991)

Method of diagnosing single bridging faults in combinational circuit. - Teruhiko Yamada; Koji Yamazaki (Syst. Comput. Jpn., 1991)

A method of diagnosing single stuck-at faults in combinational circuits. - Teruhiko Yamada; Yoshiyuki Nakamura (Syst. Comput. Jpn., 1992)

A simple technique for locating gate-level faults in combinational circuits. - Teruhiko Yamada; Koji Yamazaki; Edward J. McCluskey (Asian Test Symposium, 1995)

Accelerating the Pace of R&D in Asia. - Teruhiko Yamada (IEEE Des. Test Comput., 1995)

A Single Bridging Fault Location Technique for CMOS Combinational Circuits. - Koji Yamazaki; Teruhiko Yamada (IEICE Trans. Inf. Syst., 1995)

On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. - Teruhiko Yamada; Tsuyoshi Sasaki (Asian Test Symposium, 1996)

An approach to diagnose logical faults in partially observable sequential circuits. - Koji Yamazaki; Teruhiko Yamada (Asian Test Symposium, 1997)

On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. - Teruhiko Yamada; Tsuneto Hanashima; Yasuhiro Suemori; Masaaki Maezawa (Asian Test Symposium, 1998)

1997 Asian Test Symposium. - Teruhiko Yamada (IEEE Des. Test Comput., 1998)

Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. - Teruhiko Yamada; Toshinori Kotake; Hiroshi Takahashi; Koji Yamazaki (Asian Test Symposium, 1999)