A delay test system for high speed logic LSI's. - Kuniaki Kishida; F. Shirotori; Y. Ikemoto; Shun Ishiyama; Terumine Hayashi (DAC, 1986)

Enhanced Delay Test Generator for High-Speed Logic LSIs. - Kazumi Hatayama; Mitsuji Ikeda; Terumine Hayashi; Masahiro Takakura; Kuniaki Kishida; Shun Ishiyama (ITC, 1989)

LSI module placement methods using neural computation networks. - Hiroshi Date; Mitsuho Seki; Terumine Hayashi (IJCNN, 1990)

Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. - Yutaka Sekiyama; Yasuyuki Fujihara; Terumine Hayashi; Mitsuho Seki; Jiro Kusuhara; Kazuhiko Iijima; Masahiro Takakura; Koji Fukatani (ICCAD, 1991)

Sequential Test Generation Based on Real-Value Logic. - Kazumi Hatayama; Kazunori Hikone; Mitsuji Ikeda; Terumine Hayashi (ITC, 1992)

Sequential circuit test generation by real number simulation. - Kazunori Hikone; Mitsuji Ikeda; Kazumi Hatayama; Terumine Hayashi (Syst. Comput. Jpn., 1993)

An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. - Kai Zhang; Haruhiko Takase; Terumine Hayashi; Hidehiko Kita (ASP-DAC, 1997)

Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. - Tsuyoshi Shinogi; Terumine Hayashi; Kazuo Taki (Asian Test Symposium, 1997)

On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. - Junzhi Sang; Tsuyoshi Shinogi; Haruhiko Takase; Terumine Hayashi (Asian Test Symposium, 1998)

A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. - Tsuyoshi Shinogi; Terumine Hayashi (VTS, 1998)

A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. - Kai Zhang; Tsuyoshi Shinogi; Haruhiko Takase; Terumine Hayashi (ASP-DAC, 1999)

A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. - Tsuyoshi Shinogi; Terumine Hayashi (Asian Test Symposium, 1999)

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits. - Tsuyoshi Shinogi; Terumine Hayashi; Kazuo Taki (Syst. Comput. Jpn., 1999)

Cyclic greedy generation method for limited number of IDDQ tests. - Tsuyoshi Shinogi; Masahiro Ushio; Terumine Hayashi (Asian Test Symposium, 2000)

Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. - Haruhiko Takase; Tsuyoshi Shinogi; Terumine Hayashi; Hidehiko Kita (IJCNN (3), 2000)

Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. - Tsuyoshi Shinogi; Tomokazu Kanbayashi; Tomohiro Yoshikawa; Shinji Tsuruoka; Terumine Hayashi (Asian Test Symposium, 2001)

An enhanced fault model for high defect coverage. - Junzhi Sang; Tsuyoshi Shinogi; Haruhiko Takase; Hidehiko Kita; Terumine Hayashi (Syst. Comput. Jpn., 2001)

Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. - Tsuyoshi Shinogi; Yuki Yamada; Terumine Hayashi; Tomohiro Yoshikawa; Shinji Tsuruoka (Asian Test Symposium, 2003)

Manipulation of hidden units activities for fault tolerant multi-layer neural networks. - Yusei Katsuda; Haruhiko Takase; Hidehiko Kita; Terumine Hayashi (CIRA, 2003)

Test data compression technique using selective don't-care identification. - Terumine Hayashi; Haruna Yoshioka; Tsuyoshi Shinogi; Hidehiko Kita; Haruhiko Takase (ASP-DAC, 2004)

A study on the simple penalty term to the error function from the viewpoint of fault tolerant training. - Haruhiko Takase; Hidehiko Kita; Terumine Hayashi (IJCNN, 2004)

A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. - Tsuyoshi Shinogi; Hiroyuki Yamada; Terumine Hayashi; Shinji Tsuruoka; Tomohiro Yoshikawa (Asian Test Symposium, 2005)

Dynamic construction of fault tolerant multi-layer neural networks. - Haruhiko Takase; Ayumi Nobuto; Hidehiko Kita; Terumine Hayashi (IJCNN, 2005)

On Test Data Compression Using Selective Don't-Care Identification. - Terumine Hayashi; Haruna Yoshioka; Tsuyoshi Shinogi; Hidehiko Kita; Haruhiko Takase (J. Comput. Sci. Technol., 2005)

Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing. - Terumine Hayashi; Naotsugu Ikeda; Tsuyoshi Shinogi; Haruhiko Takase; Hidehiko Kita (ATS, 2006)

Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. - Haruhiko Takase; Hidehiko Kita; Terumine Hayashi (IJCNN, 2006)

Descriptive Answer Clustering System for Immediate Feedback. - Kazutaka Noro; Haruhiko Takase; Hidehiko Kita; Terumine Hayashi; Naoki Morita (ICCE, 2007)

Enhancing both generalization and fault tolerance of multilayer neural networks. - Haruhiko Takase; Masahiko Masahiko; Hidehiko Kita; Terumine Hayashi (IJCNN, 2007)

Shape of error surfaces in SpikeProp. - Masaru Fujita; Haruhiko Takase; Hidehiko Kita; Terumine Hayashi (IJCNN, 2008)

Obstacle to training SpikeProp networks - Cause of surges in training process -. - Haruhiko Takase; Masaru Fujita; Hiroharu Kawanaka; Shinji Tsuruoka; Hidehiko Kita; Terumine Hayashi (IJCNN, 2009)