Scalability-based manycore partitioning. - Hiroshi Sasaki 001; Teruo Tanimoto; Koji Inoue; Hiroshi Nakamura (PACT, 2012)

FlexDAS: A flexible direct attached storage for I/O intensive applications. - Takatsugu Ono; Yotaro Konishi; Teruo Tanimoto; Noboru Iwamatsu; Takashi Miyoshi; Jun Tanaka (IEEE BigData, 2014)

Hardware-assisted scalable flow control of shared receive queue. - Teruo Tanimoto; Takatsugu Ono; Kohta Nakashima; Takashi Miyoshi (ICS, 2014)

A Flexible Direct Attached Storage for a Data Intensive Application. - Takatsugu Ono; Yotaro Konishi; Teruo Tanimoto; Noboru Iwamatsu; Takashi Miyoshi; Jun Tanaka (IEICE Trans. Inf. Syst., 2015)

CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors. - Teruo Tanimoto; Takatsugu Ono; Koji Inoue (CANDAR, 2017)

Why do programs have heavy tails? - Hiroshi Sasaki 001; Fang-Hsiang Su; Teruo Tanimoto; Simha Sethumadhavan (IISWC, 2017)

Heavy Tails in Program Structure. - Hiroshi Sasaki 001; Fang-Hsiang Su; Teruo Tanimoto; Simha Sethumadhavan (IEEE Comput. Archit. Lett., 2017)

Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. - Teruo Tanimoto; Takatsugu Ono; Koji Inoue; Hiroshi Sasaki 001 (IEEE Comput. Archit. Lett., 2017)

Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors. - Teruo Tanimoto; Takatsugu Ono; Koji Inoue (J. Inf. Process., 2017)

Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution. - Teruo Tanimoto; Takatsugu Ono; Koji Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Enhancing a manycore-oriented compressed cache for GPGPU. - Keitaro Oka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Koji Inoue (HPC Asia, 2020)

How Many Trials Do We Need for Reliable NISQ Computing? - Teruo Tanimoto; Shuhei Matsuo; Satoshi Kawakami; Yutaka Tabuchi; Masao Hirokawa; Koji Inoue (ISVLSI, 2020)

Practical Error Modeling Toward Realistic NISQ Simulation. - Teruo Tanimoto; Shuhei Matsuo; Satoshi Kawakami; Yutaka Tabuchi; Masao Hirokawa; Koji Inoue (ISVLSI, 2020)

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices. - Koki Ishida; Ilkwon Byun; Ikki Nagaoka; Kosuke Fukumitsu; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Jangwoo Kim; Koji Inoue (MICRO, 2020)

32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic. - Koki Ishida; Masamitsu Tanaka; Ikki Nagaoka; Takatsugu Ono; Satoshi Kawakami; Teruo Tanimoto; Akira Fujimaki; Koji Inoue (VLSI Circuits, 2020)

Superconductor Computing for Neural Networks. - Koki Ishida; Ilkwon Byun; Ikki Nagaoka; Kosuke Fukumitsu; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Jangwoo Kim; Koji Inoue (IEEE Micro, 2021)

XQsim: modeling cross-technology control processors for 10+K qubit quantum computers. - Ilkwon Byun; Junpyo Kim; Dongmoon Min; Ikki Nagaoka; Kosuke Fukumitsu; Iori Ishikawa; Teruo Tanimoto; Masamitsu Tanaka; Koji Inoue; Jangwoo Kim (ISCA, 2022)

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. - Iori Ishikawa; Ikki Nagaoka; Ryota Kashima; Koki Ishida; Kosuke Fukumitsu; Keitaro Oka; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Akira Fujimaki; Koji Inoue (ISCAS, 2022)

Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays. - Yasunari Suzuki; Takanori Sugiyama; Tomochika Arai; Wang Liao; Koji Inoue; Teruo Tanimoto (MICRO, 2022)

An Edge Autonomous Lamp Control with Camera Feedback. - Satoshi Matsushita; Teruo Tanimoto; Satoshi Kawakami; Takatsugu Ono; Koji Inoue (WF-IoT, 2022)

WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code. - Wang Liao; Yasunari Suzuki; Teruo Tanimoto; Yosuke Ueno; Yuuki Tokunaga (ASP-DAC, 2023)

Circuit designs for practical-scale fault-tolerant quantum computing. - Yasunari Suzuki; Yosuke Ueno; Wang Liao; Masamitsu Tanaka; Teruo Tanimoto (VLSI Technology and Circuits, 2023)

Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers. - KuanYi Ng; Aalaa M. A. Babai; Teruo Tanimoto; Satoshi Kawakami; Koji Inoue (J. Inf. Process., 2023)

Low-Power Half-Flux-Quantum based Counter Circuits for Cryogenic Quantum Computers. - Yuki Matsumoto; Teruo Tanimoto; Masamitsu Tanaka; Takatsugu Ono (QCE, 2024)

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. - Yosuke Ueno; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (IEEE Comput. Archit. Lett., 2024)

SFQ counter-based precomputation for large-scale cryogenic VQE machines. - Yosuke Ueno; Satoshi Imamura; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (CoRR, 2024)

C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. - Yosuke Ueno; Satoshi Imamura; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (CoRR, 2024)

High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture. - Yosuke Ueno; Taku Saito; Teruo Tanimoto; Yasunari Suzuki; Yutaka Tabuchi; Shuhei Tamate; Hiroshi Nakamura (CoRR, 2024)

LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing. - Takumi Kobori; Yasunari Suzuki; Yosuke Ueno; Teruo Tanimoto; Synge Todo; Yuuki Tokunaga (HPCA, 2025)

Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines. - Pratiksha Mundhe; Yuta Hano; Satoshi Kawakami; Teruo Tanimoto; Masamitsu Tanaka; Koji Inoue; Ilkwon Byun (IEEE Comput. Archit. Lett., 2025)