Physical random number generator based on MOS structure after soft breakdown. - Shinichi Yasuda; Hideki Satake; Tetsufumi Tanamoto; Ryuji Ohba; Ken Uchida; Shinobu Fujita (IEEE J. Solid State Circuits, 2004)

Physical random number generators for cryptographic application in mobile devices. - Shinichi Yasuda; Tetsufumi Tanamoto; Ryuji Ohba; Keiko Abe; Hanae Nozaki; Shinobu Fujita (ESSCIRC, 2005)

Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. - Ryuji Ohba; Daisuke Matsushita; Koichi Muraoka; Shinichi Yasuda; Tetsufumi Tanamoto; Ken Uchida; Shinobu Fujita (ISVLSI, 2006)

3D Nanowire-Based Programmable Logic. - Benjamin Gojman; Raphael Rubin; Concetta Pilotto; André DeHon; Tetsufumi Tanamoto (Nano-Net, 2006)

1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. - Mari Matsumoto; Shinichi Yasuda; Ryuji Ohba; Kazutaka Ikegami; Tetsufumi Tanamoto; Shinobu Fujita (ISSCC, 2008)

Perspectives and Issues in 3D-IC from Designers' Point of View. - Shinobu Fujita; Keiko Abe; Kumiko Nomura; Shinichi Yasuda; Tetsufumi Tanamoto (ISCAS, 2009)

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). - Shinichi Yasuda; Tetsufumi Tanamoto; Kazutaka Ikegami; Atsuhiro Kinoshita; Keiko Abe; Hirotaka Nishino; Shinobu Fujita (FPGA, 2010)

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET - Tetsufumi Tanamoto; Hideyuki Sugiyama; Tomoaki Inokuchi; Takao Marukame; Mizue Ishikawa; Kazutaka Ikegami; Yoshiaki Saito (CoRR, 2011)

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. - Hiroki Noguchi; Kazutaka Ikegami; Naoharu Shimomura; Tetsufumi Tanamoto; Junichi Ito; Shinobu Fujita (VLSIC, 2014)

High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code. - Tetsufumi Tanamoto; Naoharu Shimomura; Sumio Ikegawa; Mari Matsumoto; Shinobu Fujita; Hiroaki Yoda (CoRR, 2016)

Physically Unclonable Function using Initial Waveform of Ring Oscillators. - Tetsufumi Tanamoto; Shinichi Yasuda; Satoshi Takaya; Shinobu Fujita (CoRR, 2016)

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. - Tetsufumi Tanamoto; Satoshi Takaya; Nobuaki Sakamoto; Hirotsugu Kasho; Shinichi Yasuda; Takao Marukame; Shinobu Fujita; Yuichiro Mitani (CoRR, 2017)

Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. - Tetsufumi Tanamoto; Shinichi Yasuda; Satoshi Takaya; Shinobu Fujita (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. - Tetsufumi Tanamoto; Chika Tanaka; Satoshi Takaya; Masato Koyama (IEICE Electron. Express, 2018)

SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET. - Tetsufumi Tanamoto; Chika Tanaka; Shinichi Takagi (IEICE Electron. Express, 2020)

3D Stacked Spin Qubit by TCAD Simulations. - Tetsufumi Tanamoto (3DIC, 2024)