2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell. - Hiroshige Hirano; Toshiyuki Honda; Nobuyuki Moriwaki; Tetsuji Nakakuma; Atsuo Inoue; George Nakane; Shigeo Chaya; Tatsumi Sumi (IEEE J. Solid State Circuits, 1997)

A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure. - Kunisato Yamaoka; Shunichi Iwanari; Yasuo Murakuki; Hiroshige Hirano; Masahiko Sakagami; Tetsuji Nakakuma; Takashi Miki; Yasushi Gohou (IEEE J. Solid State Circuits, 2005)