An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. - Masaki Momodomi; Yasuo Itoh; Riichiro Shirota; Yoshihisa Iwata; Ryozo Nakayama; Ryouhei Kirisawa; Tomoharu Tanaka; Seiichi Aritome; Tetsuo Endoh; Kazunori Ohuchi; Fujjo Masuoka (IEEE J. Solid State Circuits, 1989)

A high-density NAND EEPROM with block-page programming for microcomputer applications. - Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Yasuo Itoh; Ryozo Nakayama; Ryouhei Kirisawa; Seiichi Aritome; Tetsuo Endoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

Reliability issues of flash memory cells. - Seiichi Aritome; Riichiro Shirota; Gertjan Hemink; Tetsuo Endoh; Fujio Masuoka (Proc. IEEE, 1993)

New three-dimensional memory array architecture for future ultrahigh-density DRAM. - Tetsuo Endoh; Katsuhisa Shinmei; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 1999)

An on-chip 96.5% current efficiency CMOS linear regulator. - Kazuhisa Sunaga; Tetsuo Endoh; Hiroshi Sakuraba; Fujio Masuoka (ASP-DAC, 2001)

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. - Tetsuo Endoh; Kazuhisa Sunaga; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. - Akira Tanabe; Masato Umetani; Ikuo Fujiwara; Takayuki Ogura; Kotaro Kataoka; Masao Okihara; Hiroshi Sakuraba; Tetsuo Endoh; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films. - Tetsuo Endoh; Kazuyuki Hirose; Kenji Shiraishi (IEICE Trans. Electron., 2007)

Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator. - Tetsuo Endoh; Yuto Momma (IEICE Trans. Electron., 2007)

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. - Shoun Matsunaga; Jun Hayakawa; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (DATE, 2009)

Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch. - Tetsuo Endoh; Masashi Kamiyanagi (IEICE Trans. Electron., 2009)

Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism. - Tetsuo Endoh; Yuto Norifusa (IEICE Trans. Electron., 2009)

Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor. - Tetsuo Endoh; Yuto Norifusa (IEICE Trans. Electron., 2009)

A compact and low power logic design for multi-pillar vertical MOSFETs. - Koji Sakui; Tetsuo Endoh (ISCAS, 2010)

Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure. - Tetsuo Endoh; Koji Sakui; Yukio Yasuda (IEICE Trans. Electron., 2010)

Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET. - Tetsuo Endoh; Koji Sakui; Yukio Yasuda (IEICE Trans. Electron., 2010)

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. - Fumitaka Iga; Masashi Kamiyanagi; Shoji Ikeda; Katsuya Miura; Jun Hayakawa; Haruhiro Hasegawa; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEICE Trans. Electron., 2010)

Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. - Masashi Kamiyanagi; Fumitaka Iga; Shoji Ikeda; Katsuya Miura; Jun Hayakawa; Haruhiro Hasegawa; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEICE Trans. Electron., 2010)

Study on Quantum Electro-Dynamics in Vertical MOSFET. - Masakazu Muraguchi; Tetsuo Endoh (IEICE Trans. Electron., 2010)

Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot. - Masakazu Muraguchi; Yukihiro Takada; Shintaro Nomura; Tetsuo Endoh; Kenji Shiraishi (IEICE Trans. Electron., 2010)

A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. - Yitao Ma; Tetsuo Endoh; Tadashi Shibata (ISOCC, 2011)

The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation. - Tetsuo Endoh; Masashi Kamiyanagi; Masakazu Muraguchi; Takuya Imamoto; Takeshi Sasaki (IEICE Trans. Electron., 2011)

Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process. - Takuya Imamoto; Takeshi Sasaki; Tetsuo Endoh (IEICE Trans. Electron., 2011)

Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation. - Masashi Kamiyanagi; Takuya Imamoto; Takeshi Sasaki; Hyoungjun Na; Tetsuo Endoh (IEICE Trans. Electron., 2011)

Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET. - Masakazu Muraguchi; Tetsuo Endoh (IEICE Trans. Electron., 2011)

Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor. - Masakazu Muraguchi; Yoko Sakurai; Yukihiro Takada; Shintaro Nomura; Kenji Shiraishi; Mitsuhisa Ikeda; Katsunori Makihara; Seiichi Miyazaki; Yasuteru Shigeta; Tetsuo Endoh (IEICE Trans. Electron., 2011)

Impact of Floating Body Type DRAM with the Vertical MOSFET. - Yuto Norifusa; Tetsuo Endoh (IEICE Trans. Electron., 2011)

Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit. - Takeshi Sasaki; Takuya Imamoto; Tetsuo Endoh (IEICE Trans. Electron., 2011)

The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure. - Moon-Sik Seo; Tetsuo Endoh (IEICE Trans. Electron., 2011)

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. - Shoun Matsunaga; Masanori Natsui; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (ASP-DAC, 2012)

High-speed simulator including accurate MTJ models for spintronics integrated circuit design. - Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Hiroaki Honjo; Tadahiko Sugibayashi; Hiroki Koike; Takashi Ohsawa; Shunsuke Fukami; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (ISCAS, 2012)

A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. - Shoun Matsunaga; Sadahiko Miura; Hiroaki Honjou; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2012)

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keiichi Tokutome; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (VLSIC, 2012)

Source/Drain Engineering for High Performance Vertical MOSFET. - Takuya Imamoto; Tetsuo Endoh (IEICE Trans. Electron., 2012)

Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation. - Hyoungjun Na; Tetsuo Endoh (IEICE Trans. Electron., 2012)

A Schmitt Trigger Based SRAM with Vertical MOSFET. - Hyoungjun Na; Tetsuo Endoh (IEICE Trans. Electron., 2012)

Evaluation of Performance in Vertical 1T-DRAM and Planar 1T-DRAM. - Yuto Norifusa; Tetsuo Endoh (IEICE Trans. Electron., 2012)

FG Width Scalability of the 3-D Vertical FG NAND Using the Sidewall Control Gate (SCG). - Moon-Sik Seo; Tetsuo Endoh (IEICE Trans. Electron., 2012)

Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating. - Shuta Togashi; Takashi Ohsawa; Tetsuo Endoh (IEICE Trans. Electron., 2012)

An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. - Yitao Ma; Tadashi Shibata; Tetsuo Endoh (ISCAS, 2013)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

Foreword. - Tetsuo Endoh (IEICE Trans. Electron., 2013)

A High Performance Current Latch Sense Amplifier with Vertical MOSFET. - Hyoungjun Na; Tetsuo Endoh (IEICE Trans. Electron., 2013)

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEEE J. Solid State Circuits, 2013)

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; et al. (ISCAS, 2014)

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. - Noboru Sakimura; Yukihide Tsuji; Ryusuke Nebashi; Hiroaki Honjo; Ayuka Morioka; Kunihiko Ishihara; Keizo Kinoshita; Shunsuke Fukami; Sadahiko Miura; Naoki Kasai; Tetsuo Endoh; Hideo Ohno; et al. (ISSCC, 2014)

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Noboru Sakimura; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. - Shoun Matsunaga; Akira Mochizuki; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. - Shoun Matsunaga; Akira Mochizuki; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. - Daisuke Suzuki; Noboru Sakimura; Masanori Natsui; Akira Mochizuki; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

A Novel Alternating Voltage Controlled Current Sensing Method for Suppressing Thermal Dependency. - Kazuki Itoh; Tetsuo Endoh (IEICE Trans. Electron., 2014)

A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. - Satoru Tanoi; Tetsuo Endoh (IEICE Trans. Electron., 2014)

Nonvolatile logic and memory devices based on spintronics. - Tetsuo Endoh (ISCAS, 2015)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. - Masanori Natsui; Akira Tamakoshi; Akira Mochizuki; Hiroki Koike; Hideo Ohno; Tetsuo Endoh; Takahiro Hanyu (ISCAS, 2016)

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. - Tetsuo Endoh; Hiroki Koike; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Formation mechanism of concave by dielectric breakdown on silicon carbide metal-oxide-semiconductor capacitor. - Soshi Sato; Kikuo Yamabe; Tetsuo Endoh; Masaaki Niwa (Microelectron. Reliab., 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs. - Tetsuo Endoh (VLSI-DAT, 2017)

Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. - Ryo Tamura; I. Mori; N. Watanabe; Hiroki Koike; Tetsuo Endoh (NVMTS, 2018)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A novel memory test system with an electromagnet for STT-MRAM testing. - Ryo Tamura; N. Watanabe; Hiroki Koike; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Soshi Sato (NVMTS, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application. - Tao Li 005; Yitao Ma; Tetsuo Endoh (IEEE Access, 2020)

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate. - Tao Li 005; Yitao Ma; Tetsuo Endoh (IEEE Access, 2020)

FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering. - Tao Li 005; Yitao Ma; Hui Shen; Tetsuo Endoh (IEEE Trans. Veh. Technol., 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. - K. Watanabe; T. Shimada; K. Hirose; H. Shindo; D. Kobayashi; Takaho Tanigawa; Shoji Ikeda; Takamitsu Shinada; Hiroki Koike; Tetsuo Endoh; T. Makino; Takeshi Ohshima (IRPS, 2022)

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. - Tao Li 005; Yitao Ma; Ko Yoshikawa; Osamu Nomura; Tetsuo Endoh (IEEE Trans. Ind. Informatics, 2022)

Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. - Tao Li 005; Yitao Ma; Ko Yoshikawa; Tetsuo Endoh (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3. - Tao Li 005; Yitao Ma; Tetsuo Endoh (Neural Comput. Appl., 2023)

Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". - Tao Li 005; Yitao Ma; Ko Yoshikawa; Tetsuo Endoh (IEEE Trans. Very Large Scale Integr. Syst., 2023)

From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society. - Tao Li 005; Yitao Ma; Tetsuo Endoh (IEEE Trans. Ind. Informatics, 2023)

Small Area and High Throughput Error Correction Module of STT-MRAM for Object Recognition Systems. - Li Zhang; Tao Li 005; Tetsuo Endoh (IEEE Trans. Ind. Informatics, 2024)

Memristor State Transition Dynamics for Energy-Efficient CiM-Driven LLMs in Industrial IoT. - Tao Li 005; Tetsuo Endoh (IEEE Internet Things J., 2025)