Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. - Tetsuo Hironaka; Takashi Hashimoto; Keizo Okazaki; Kazuaki J. Murakami; Shinji Tomita (ICS, 1992)

A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. - Takashi Hashimoto; Kazuaki J. Murakami; Tetsuo Hironaka; Hiroto Yasuura (International Conference on Supercomputing, 1993)

Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. - Naoki Nishimura; Takahiro Sasaki; Tetsuo Hironaka (ASP-DAC, 2000)

Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling. - Takahiro Sasaki; Tetsuo Hironaka; Seiji Fujino (Informatica (Slovenia), 2000)

A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. - Kazuya Tanigawa; Tetsuo Hironaka; Akira Kojima; Noriyoshi Yoshida (FPL, 2002)

A novel hierarchical multi-port cache. - Zhaomin Zhu; Koh Johguchi; Hans Jürgen Mattausch; Tetsushi Koide; Tai Hirakawa; Tetsuo Hironaka (ESSCIRC, 2003)

A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. - Kazuya Tanigawa; Takashi Kawasaki; Tetsuo Hironaka (FPT, 2003)

Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. - Tetsuya Sueyoshi; Hiroshi Uchida; Hans Jürgen Mattausch; Tetsushi Koide; Yosuke Mitani; Tetsuo Hironaka (ASP-DAC, 2004)

Design of superscalar processor with multi-bank register file. - Tadashi Saito 002; Moto Maeda; Tetsuo Hironaka; Kazuya Tanigawa; Tetsuya Sueyoshi; Ken-ichi Aoyama; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS (4), 2005)

Chip size and performance evaluations of shared cache for on-chip multiprocessor. - Takahiro Sasaki; Tomohiro Inoue; Nobuhiko Omori; Tetsuo Hironaka; Hans Jürgen Mattausch; Tetsushi Koide (Syst. Comput. Jpn., 2005)

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. - Koh Johguchi; Zhaomin Zhu; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka; Kazuya Tanigawa (APCCAS, 2006)

Scheduling support hardware for multiprocessor system and its evaluations. - Takahiro Sasaki; Tetsuo Hironaka; Naoki Nishimura; Noriyoshi Yoshida (Syst. Comput. Jpn., 2006)

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. - Koh Johguchi; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka (IEICE Trans. Electron., 2007)

Exploring compact design on high throughput coarse grained reconfigurable architectures. - Kazuya Tanigawa; Tetsuya Zuyama; Takuro Uchida; Tetsuo Hironaka (FPL, 2008)

Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. - Kazuya Tanigawa; Tetsuo Hironaka (FPT, 2008)

Evaluation of low-energy and high-performance processor using variable stages pipeline technique. - Takahiro Sasaki; Yuji Ichikawa; Tetsuo Hironaka; Toshiaki Kitamura; Toshio Kondo (IET Comput. Digit. Tech., 2008)

Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. - Kazuya Tanigawa; Ken'ichi Umeda; Tetsuo Hironaka (ARC, 2010)

Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. - Kazuya Tanigawa; Tetsuo Hironaka (ISOCC, 2011)

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. - Masatoshi Nakamura; Masato Inagi; Kazuya Tanigawa; Tetsuo Hironaka; Masayuki Sato; Takashi Ishiguro (ReConFig, 2011)

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. - Masatoshi Nakamura; Masato Inagi; Kazuya Tanigawa; Tetsuo Hironaka; Masayuki Sato; Takashi Ishiguro (IEICE Trans. Inf. Syst., 2012)

Foreword. - Tetsuo Hironaka (IEICE Trans. Inf. Syst., 2015)

Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof General. - Hideyuki Kawabata; Yuta Tanaka; Mai Kimura; Tetsuo Hironaka (APLAS, 2018)

OSAIFU: A Source Code Factorizer on Android Studio. - Masahiro Hata; Masashi Nishimoto; Keiji Nishiyama; Hideyuki Kawabata; Tetsuo Hironaka (ICSME, 2019)

Extracting Inclusion Graphs of API Member Sets to Improve Searchability. - Yushi Kondoh; Masashi Nishimoto; Keiji Nishiyama; Hideyuki Kawabata; Tetsuo Hironaka (SERA, 2019)

Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. - Masashi Nishimoto; Keiji Nishiyama; Hideyuki Kawabata; Tetsuo Hironaka (SERA, 2019)

Efficient Searching for Essential API Member Sets based on Inclusion Relation Extraction. - Yushi Kondoh; Masashi Nishimoto; Keiji Nishiyama; Hideyuki Kawabata; Tetsuo Hironaka (Int. J. Networked Distributed Comput., 2019)

SAIFU: Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. - Masashi Nishimoto; Keiji Nishiyama; Hideyuki Kawabata; Tetsuo Hironaka (Int. J. Networked Distributed Comput., 2019)

Resolving Ambiguous Types in Haskell by Checking Uniqueness of Type Variable Assignments under Type Class Constraints. - Yuya Kono; Hideyuki Kawabata; Tetsuo Hironaka (J. Inf. Process., 2019)

Easy-going Development of Event-Driven Applications by Iterating a Search-Select-Superpose Loop. - Masashi Nishimoto; Keiji Nishiyama; Hideyuki Kawabata; Tetsuo Hironaka (J. Inf. Process., 2019)

Rumpfr: A Fast and Memory Leak-free Rust Binding to the GNU MPFR Library. - Tomoya Michinaka; Hideyuki Kawabata; Tetsuo Hironaka (J. Inf. Process., 2021)