Low-power SRAM design using half-swing pulse-mode techniques. - Kenneth W. Mai; Toshihiko Mori; Bharadwaj S. Amrutur; Ron Ho; Bennett Wilburn; Mark A. Horowitz; Isao Fukushi; Tetsuo Izawa; Shin Mitarai (IEEE J. Solid State Circuits, 1998)

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. - Yisuo Li; Ken'ichi Kanazawa; Tetsuo Izawa; Koji Sakui; Georg Strof; Oskar Baumgartner; Gerhard Rzepa; Markus Karner; Zlatan Stanojevic; Nozomu Harada; Fujio Masuoka (IMW, 2021)