A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mikio Asakura; Kenichi Yasuda; Kiyohiro Furutani; Tetsuo Kato; Hideto Hidaka; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1996)

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. - Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; et al. (IEEE J. Solid State Circuits, 2000)