Quantum gauged neural networks: learning and recalling. - Yukari Fujita; Takashi Hiramatsu; Tetsuo Matsui (IJCNN, 2005)

Asymmetric Synaptic Connections in Z(2) Gauge Neural Network. - Atsutomo Murai; Tetsuo Matsui (ICONIP (4), 2016)

Neural Network for Quantum Brain Dynamics: 4D CP ^1 1 +U(1) Gauge Theory on Lattice and Its Phase Structure. - Shinya Sakane; Takashi Hiramatsu; Tetsuo Matsui (ICONIP (1), 2016)

Gauge Neural Network with Z(2) Synaptic Variables: Phase Structure and Simulation of Learning and Recalling Patterns. - Atsutomo Murai; Tetsuo Matsui (Neural Process. Lett., 2018)

A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller. - Tetsuo Matsui; Keisaku Sento; Tomohiko Ebata; Atsuhiko Ishibashi (ESSCIRC, 2019)

9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS. - Mitsuya Fukazawa; Takashi Oshima; Masaki Fujiwara; Katsuki Tateyama; Alsubaie Raed; Masao Ito; Tetsuya Matsumoto; Tetsuo Matsui (ISSCC, 2020)

A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction. - Mitsuya Fukazawa; Takashi Oshima; Masaki Fujiwara; Katsuki Tateyama; Atsushi Ochi; Alsubaie Raed; Tetsuo Matsui (IEEE J. Solid State Circuits, 2021)

A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer. - Mitsuya Fukazawa; Tetsuo Matsui (VLSI Technology and Circuits, 2023)

A 16-bit SAR ADC with Capacitor Dielectric Relaxation Effect Canceler in a 22-nm Microcontroller for Multi-Input Channel Applications. - Tomohiko Ebata; Atsushi Ochi; Iori Sakai; Cheng Yuan; Takanobu Nimiya; Daiki Matsumoto; Qiaoyu Wang; Shinsuke Yoshimura; Tetsuo Matsui (A-SSCC, 2024)