A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. - Narumi Sakashita; Fumihiro Okuda; Ken'ichi Shimomura; Hiroki Shimano; Mitsuhiro Hamada; Tetsuo Tada; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; Haruhiko Abe (ITC, 1996)

Test cost reduction by at-speed BISR for embedded DRAMs. - Yoshihiro Nagura; Michael Mullins; Anthony Sauvageau; Yoshinoro Fujiwara; Katsuya Furue; Ryuji Ohmura; Tatsunori Komoike; Takenori Okitaka; Tetsushi Tanizaki; Katsumi Dosaka; Kazutami Arimoto; Yukiyoshi Koda; et al. (ITC, 2001)

Opportunities with the open architecture test system. - Tetsuo Tada (ASP-DAC, 2004)

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. - Masaki Hashizume; Daisuke Yoneda; Hiroyuki Yotsuyanagi; Tetsuo Tada; Takeshi Koyama; Ikuro Morita; Takeomi Tamesada (Asian Test Symposium, 2004)