Effective Vectorization Techniques for Circuit Analyses on a Vector Computer. - Tetsuro Kage; Shintaro Shimogori (Syst. Comput. Jpn., 1988)

A precise event-driven circuit simulator based on predicted fan-in voltages. - Hisanori Fujisawa; Fumiyo Kawafuji; Tomoyasu Kitaura; Tetsuro Kage (ED&TC, 1995)

DEPOGIT: dense power-ground interconnect architecture for physical design integrity. - Atsushi Kurokawa; Nobuto Ono; Tetsuro Kage; Hiroo Masuda (ASP-DAC, 2004)

Large-scale linear circuit simulation with an inversed inductance matrix. - Chieki Mizuta; Jiro Iwai; Ken Machida; Tetsuro Kage; Hiroo Masuda (ASP-DAC, 2004)

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. - Atsushi Kurokawa; Toshiki Kanamoto; Tetsuya Ibe; Akira Kasebe; Wei Fong Chang; Tetsuro Kage; Yasuaki Inoue; Hiroo Masuda (ISQED, 2005)

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. - Atsushi Kurokawa; Masaharu Yamamoto; Nobuto Ono; Tetsuro Kage; Yasuaki Inoue; Hiroo Masuda (ISQED, 2005)

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. - Atsushi Kurokawa; Toshiki Kanamoto; Tetsuya Ibe; Akira Kasebe; Wei Fong Chang; Tetsuro Kage; Yasuaki Inoue; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)