Frequency Response Analysis of Latch Utilized in High-Speed Comparator. - Shunsuke Okura; Tetsuro Okura; Kenji Taniguchi 001; Hajime Shibata (ICECS, 2006)

A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC. - Shunsuke Okura; Tetsuro Okura; Indika U. K. Bogoda Appuhamylage; Kenji Taniguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter. - Shunsuke Okura; Tetsuro Okura; Toru Ido; Kenji Taniguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Frequency Model of a Continuously Driven Clocked CMOS Comparator. - Shunsuke Okura; Hajime Shibata; Tetsuro Okura; Toru Ido; Kenji Taniguchi 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A low-power technique for pipelined ADCs with programmable gain amplification. - Tetsuro Okura; Shunsuke Okura; Toshimasa Matsuoka; Kenji Taniguchi 001 (IEICE Electron. Express, 2013)