An optimal channel pin assignment with multiple intervals for building block layout. - Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (EURO-DAC, 1992)

A new global routing algorithm for over-the-cell routing in standard cell layouts. - Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (EURO-DAC, 1993)

Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. - Shin'ichi Wakabayashi; Hiroshi Kusumoto; Hideki Mishima; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1993)

A Floorplanning Method with Topological Constraint Manipulation. - Tetsushi Koide; Yoshinori Katsura; Katsumi Yamatani; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ISCAS, 1994)

A Systolic Graph Partitioning Algorithm for VLSI Design. - Shin'ichi Wakabayashi; Kazunori Isomoto; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1994)

A new system partitioning method under performance and physical constraints for multi-chip modules. - Yoshinori Katsura; Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ASP-DAC, 1995)

A new performance driven placement method with the Elmore delay model for row based VLSIs. - Tetsushi Koide; Mitsuhiro Ono; Shin'ichi Wakabayashi; Yutaka Nishimaru (ASP-DAC, 1995)

A three-layer over-cell multi-channel routing method for a new cell model. - Masahiro Tsuchiya; Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ASP-DAC, 1995)

An MCM Routing Algorithm Considering Crosstalk. - Tetsuya Miyoshi; Shin'ichi Wakabayashi; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1995)

A Verification Algorithm for Logic Circuits with Internal Variables. - Toshihiro Nakaoa; Shin'ichi Wakabayashi; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1995)

A three-layer over-the-cell multi-channel router for a new cell model. - Tetsushi Koide; Masahiro Tsuchiya; Shin'ichi Wakabayashi; Noriyoshi Yoshida (Integr., 1996)

Pin assignment with global routing for VLSI building block layout. - Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. - Tetsushi Koide; Mitsuhiro Ono; Shin'ichi Wakabayashi; Yutaka Nishimaru (ASP-DAC, 1997)

A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. - Tetsushi Koide; Shin'ichi Wakabayashi; Mitsuhiro Ono; Yutaka Nishimaru; Noriyoshi Yoshida (Integr., 1997)

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. - Tetsushi Koide; Shin'ichi Wakabayashi (ASP-DAC, 1998)

Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. - Koichi Hatta; Masashige Suzuki; Shin'ichi Wakabayashi; Tetsushi Koide (PPSN, 1998)

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. - Koichi Hatta; Shin'ichi Wakabayashi; Tetsushi Koide (ASP-DAC, 1999)

An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. - Shin'ichi Wakabayashi; Tetsushi Koide; Naoyoshi Toshine; Mutsuaki Goto; Yoshikatsu Nakayama; Koichi Hatta (ASP-DAC, 1999)

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. - Tetsushi Koide; Shin'ichi Wakabayashi (Integr., 1999)

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. - Takahiro Deguchi; Tetsushi Koide; Shin'ichi Wakabayashi (ASP-DAC, 2000)

Genetic algorithm accelerator GAA-II. - Shin'ichi Wakabayashi; Tetsushi Koide; Naoyoshi Toshine; Masataka Yamane; Hajime Ueno (ASP-DAC, 2000)

An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. - Shingo Nakaya; Tetsushi Koide; Shin'ichi Wakabayashi (ISCAS, 2000)

Topological optimization with a network reliability constraint. - Tetsushi Koide; S. Shinmori; H. Ishii (Discret. Appl. Math., 2001)

Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. - Koichi Hatta; Shin'ichi Wakabayashi; Tetsushi Koide (Syst. Comput. Jpn., 2001)

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. - Shinya Yamasaki; Shingo Nakaya; Shin'ichi Wakabayashi; Tetsushi Koide (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. - Hans Jürgen Mattausch; Takayuki Gyohten; Yoshihiro Soda; Tetsushi Koide (IEEE J. Solid State Circuits, 2002)

A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. - Shigeki Takekawa; Shin'ichi Wakabayashi; Tetsushi Koide (Syst. Comput. Jpn., 2002)

A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. - Tetsushi Koide; Hans Jürgen Mattausch; Yuji Yano; Takayuki Gyohten; Yoshihiro Soda (ASP-DAC, 2003)

A novel hierarchical multi-port cache. - Zhaomin Zhu; Koh Johguchi; Hans Jürgen Mattausch; Tetsushi Koide; Tai Hirakawa; Tetsuo Hironaka (ESSCIRC, 2003)

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. - Takashi Morimoto; Yohmei Harada; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2004)

Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. - Tetsuya Sueyoshi; Hiroshi Uchida; Hans Jürgen Mattausch; Tetsushi Koide; Yosuke Mitani; Tetsuo Hironaka (ASP-DAC, 2004)

Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. - Yuji Yano; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2004)

Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. - Takashi Morimoto; Yohmei Harada; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2004)

A low-power video segmentation LSI with boundary-active-only architecture. - Takashi Morimoto; Osamu Kiriyama; Hidekazu Adachi; Zhaomin Zhu; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2005)

A parallel hardware design for parametric active contour models. - Ali Ahmadi; Md. Anwarul Abedin; Hans Jürgen Mattausch; Tetsushi Koide (AVSS, 2005)

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. - Takeshi Kumaki; Yasuto Kuroda; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS (5), 2005)

Object tracking in video pictures based on image segmentation and pattern matching. - Takashi Morimoto; Osamu Kiriyama; Yohmei Harada; Hidekazu Adachi; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS (4), 2005)

Design of superscalar processor with multi-bank register file. - Tadashi Saito 002; Moto Maeda; Tetsuo Hironaka; Kazuya Tanigawa; Tetsuya Sueyoshi; Ken-ichi Aoyama; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS (4), 2005)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. - Kazunari Inoue; Hideyuki Noda; Kazutami Arimoto; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Trans. Electron., 2005)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. - Hideyuki Noda; Kazunari Inoue; Hans Jürgen Mattausch; Tetsushi Koide; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

Chip size and performance evaluations of shared cache for on-chip multiprocessor. - Takahiro Sasaki; Tomohiro Inoue; Nobuhiko Omori; Tetsuo Hironaka; Hans Jürgen Mattausch; Tetsushi Koide (Syst. Comput. Jpn., 2005)

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. - Md. Anwarul Abedin; Yuki Tanaka; Ali Ahmadi; Tetsushi Koide; Hans Jürgen Mattausch (APCCAS, 2006)

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. - Koh Johguchi; Zhaomin Zhu; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka; Kazuya Tanigawa (APCCAS, 2006)

Application of Multi-ported CAM for Parallel Coding. - Takeshi Kumaki; Y. Kouno; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch (APCCAS, 2006)

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. - Takashi Morimoto; Hidekazu Adachi; Kousuke Yamaoka; Kazutoshi Awane; Tetsushi Koide; Hans Jürgen Mattausch (APCCAS, 2006)

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. - Kousuke Yamaoka; Takashi Morimoto; Hidekazu Adachi; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2006)

A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. - Ali Ahmadi; M. Arifin Ritonga; Md. Anwarul Abedin; Hans Jürgen Mattausch; Tetsushi Koide (IEEE Congress on Evolutionary Computation, 2006)

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. - Kousuke Yamaoka; Takashi Morimoto; Hidekazu Adachi; Kazutoshi Awane; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS, 2006)

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. - Takashi Morimoto; Hidekazu Adachi; Osamu Kiriyama; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2006)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. - Hideyuki Noda; Katsumi Dosaka; Hans Jürgen Mattausch; Tetsushi Koide; Fukashi Morishita; Kazutami Arimoto (IEICE Trans. Electron., 2006)

A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. - Koh Johguchi; Yuya Mukuda; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide (ESSCIRC, 2007)

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS, 2007)

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. - Koh Johguchi; Yuya Mukuda; Ken-ichi Aoyama; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Electron. Express, 2007)

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. - Md. Anwarul Abedin; Yuki Tanaka; Ali Ahmadi; Shogo Sakakibara; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. - Koh Johguchi; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka (IEICE Trans. Electron., 2007)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. - Takeshi Kumaki; Yutaka Kono; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2007)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. - Takeshi Kumaki; Yasuto Kuroda; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. - Hans Jürgen Mattausch; Wataru Imafuku; Tania Ansari; Akio Kawabata; Tetsushi Koide (ESSCIRC, 2010)

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. - Akio Kawabata; Tetsushi Koide; Hans Jürgen Mattausch (ICNC, 2010)

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. - Tetsushi Koide; R. Kimura; T. Sugahara; K. Okazaki; Hans Jürgen Mattausch (ICNC, 2010)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)

Measurement-Based Ring Oscillator Variation Analysis. - Koh Johguchi; Akihiro Kaya; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide; Norio Sadachika (IEEE Des. Test Comput., 2010)

Real-time hybrid learning and recognition system with software-hardware cooperation. - Fengwei An; Hans Jürgen Mattausch; Tetsushi Koide (ROBIO, 2011)

An associative memory-based learning model with an efficient hardware implementation in FPGA. - Ali Ahmadi; Hans Jürgen Mattausch; Md. Anwarul Abedin; Mahmoud Saeidi; Tetsushi Koide (Expert Syst. Appl., 2011)

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Masaharu Tagami; Masakatsu Ishizaki (IEICE Trans. Inf. Syst., 2011)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. - Fengwei An; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2012)

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. - Hans Jürgen Mattausch; Wataru Imafuku; Akio Kawabata; Tania Ansari; Masahiro Yasuda; Tetsushi Koide (IEEE J. Solid State Circuits, 2012)

Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM. - Tsubasa Hirakawa; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeta Yoshida; Yoko Kominami; Taiji Matsuo; Rie Miyaki; Shinji Tanaka (EMBC, 2013)

Power electronics education using the integrated circuit consistent education system and TCAD. - Keisuke Konishi; Takeshi Tanaka; Tetsushi Koide (FIE, 2013)

Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition. - Tsubasa Hirakawa; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Yoko Kominami; Rie Miyaki; Taiji Matsuo; Shigeto Yoshida; Shinji Tanaka (ICIP, 2013)

Low cost hardware implementation for traffic sign detection system. - Anh-Tuan Hoang; Tetsushi Koide; Masaharu Yamamoto (APCCAS, 2014)

FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification. - Tetsushi Koide; Anh-Tuan Hoang; Takumi Okamoto; Satoshi Shigemi; Tsubasa Mishima; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Yoko Kominami; Rie Miyaki; Taiji Matsuo; Shigeto Yoshida; et al. (APCCAS, 2014)

Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. - Takeshi Kumaki; Takeshi Fujino; Tetsushi Koide (APCCAS, 2014)

SVM-MRF segmentation of colorectal NBI endoscopic images. - Tsubasa Hirakawa; Tom Tamaki; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Yoko Kominami; Shigeto Yoshida; Shinji Tanaka (EMBC, 2014)

Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. - Anh-Tuan Hoang; Tetsushi Koide; Masaharu Yamamoto; Mutsumi Omori (ISCAS, 2014)

FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. - Tsubasa Mishima; Satoshi Shigemi; Anh-Tuan Hoang; Tetsushi Koide; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Yoko Kominami; Rie Miyaki; Taiji Matsuo; Shigeto Yoshida; Shinji Tanaka (ISCAS, 2014)

Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. - Masaharu Yamamoto; Anh-Tuan Hoang; Mutsumi Omori; Tetsushi Koide (ISCAS, 2014)

Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images. - Takumi Okamoto; Tetsushi Koide; Koki Sugi; Tatsuya Shimizu; Anh-Tuan Hoang; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Yoko Kominami; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (EMBC, 2015)

Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification. - Shoji Sonoyama; Tsubasa Hirakawa; Toru Tamaki; Takio Kurita; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Yoko Kominami; Shinji Tanaka (EMBC, 2015)

Trade-off between speed and performance for colorectal endoscopic NBI image classification. - Shoji Sonoyama; Toru Tamaki; Tsubasa Hirakawa; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Yoko Kominami; Shigeto Yoshida; Shinji Tanaka (Image Processing, 2015)

Discriminative Subtree Selection for NBI Endoscopic Image Labeling. - Tsubasa Hirakawa; Toru Tamaki; Takio Kurita; Bisser Raytchev; Kazufumi Kaneda; Chaohui Wang; Laurent Najman; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (ACCV Workshops (2), 2016)

Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition. - Tsubasa Hirakawa; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Yoko Kominami; Shinji Tanaka (Artif. Intell. Medicine, 2016)

Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]. - Tsubasa Hirakawa; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Yoko Kominami; Shinji Tanaka (Artif. Intell. Medicine, 2016)

Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy. - Tsubasa Hirakawa; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (CoRR, 2016)

Transfer Learning for Endoscopic Image Classification. - Shoji Sonoyama; Toru Tamaki; Tsubasa Hirakawa; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (CoRR, 2016)

Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features. - Toru Tamaki; Shoji Sonoyama; Tsubasa Hirakawa; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (CoRR, 2016)

Domain Adaptation with L2 constraints for classifying images from different endoscope systems. - Toru Tamaki; Shoji Sonoyama; Takio Kurita; Tsubasa Hirakawa; Bisser Raytchev; Kazufumi Kaneda; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka; Kazuaki Chayama (CoRR, 2016)

Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM. - Takumi Okamoto; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Hiroshi Toishi; Takayuki Sugawara; Masayuki Tsuji; Masayuki Odagawa; Nobuo Tamba; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; et al. (TENCON, 2018)

An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture. - Takumi Okamoto; Yasunori Sakane; Tetsushi Koide; Atsushi Ogawa; Masashi Komine; Chiharu Sone; Yoshihiro Kaneta; Yukio Yaji; Kyoko Toyofuku; Takahiro Kamata; Ken Kimura; Yoko Ishikawa; et al. (TENCON, 2018)

A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System. - Masayuki Odagawa; Takumi Okamoto; Tetsushi Koide; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka; Takayuki Sugawara; Hiroshi Toishi; Masayuki Tsuji; et al. (ISCAS, 2019)

An IoT-gateway with the information-centric communication. - Kazunari Inoue; Nozomi Kobori; Atsushi Hirota; Tetsushi Koide; Takumi Okamoto (ISDCS, 2019)

Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection. - Kyosuke Kageyama; Takeshi Kumaki; Tetsushi Koide (ISDCS, 2019)

Low Cost and Robust Field-Deployable Environmental Sensor for Smart Agriculture. - Toshihiro Kasama; Tetsushi Koide; Wojciech P. Bula; Yukio Yaji; Yoshishige Endo; Ryo Miyake (ISDCS, 2019)

Development of In-situ Monitoring System for Crop Growth Observation. - Hideki Murakami; Yoshiki Tanaka; Jun-ichi Yamashita; Rikako Takeshita; Yasunori Sakane; Takumi Okamoto; Tetsushi Koide (ISDCS, 2019)

Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN. - Takumi Okamoto; Masayuki Odagawa; Tetsushi Koide; Shinji Tanaka; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Shigeto Yoshida; Hiroshi Mieno (ISDCS, 2019)

Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core. - Kyosuke Kageyama; Kensuke Watanabe; Akimitsu Hamai; Takeshi Kumaki; Tetsushi Koide (MWSCAS, 2020)

Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy. - Masayuki Odagawa; Takumi Okamoto; Tetsushi Koide; Shigeto Yoshida; Hiroshi Mieno; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Shinji Tanaka (TENCON, 2020)

Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis. - Tetsushi Koide; Ryuichi Michida; Seiji Izakura; Yuki Hayashida; Yumi Aoyama (MWSCAS, 2021)

An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique. - Ryuichi Michida; Seiji Izakura; Tetsushi Koide; Yuki Hayashida; Yumi Aoyama (MWSCAS, 2021)

A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System. - Masayuki Odagawa; Takumi Okamoto; Tetsushi Koide; Toru Tamaki; Bisser Raytchev; Kazufumi Kaneda; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka; Takayuki Sugawara; Hiroshi Toishi; Masayuki Tsuji; et al. (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores. - Masayuki Odagawa; Tetsushi Koide; Toru Tamaki; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image. - Masayuki Odagawa; Takumi Okamoto; Tetsushi Koide; Toru Tamaki; Shigeto Yoshida; Hiroshi Mieno; Shinji Tanaka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)