Test cost reduction by at-speed BISR for embedded DRAMs. - Yoshihiro Nagura; Michael Mullins; Anthony Sauvageau; Yoshinoro Fujiwara; Katsuya Furue; Ryuji Ohmura; Tatsunori Komoike; Takenori Okitaka; Tetsushi Tanizaki; Katsumi Dosaka; Kazutami Arimoto; Yukiyoshi Koda; et al. (ITC, 2001)

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. - Yasuhiko Taito; Tetsushi Tanizaki; Mitsuya Kinoshita; Futoshi Igaue; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 2003)

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Tetsushi Tanizaki; Takashi Ipposhi; Katsumi Dosaka (CICC, 2006)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)