A MOS circuit for a nonmonotonic neural network with excellent retrieval capabilities. - Tetsuya Asai; Hideyo Yokotsuka; Tomoki Fukai (IEEE Trans. Neural Networks, 1996)

An analog integrated circuit for motion detection. - Hiroo Yonezu; Tetsuya Asai; Masahiro Ohtani; Jang-Kyoo Shin; Naoki Ohshima (KES (3), 1998)

A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution. - Tetsuya Asai; Tomoki Fukai; Shigeru Tanaka (Neural Networks, 1999)

Analog integrated circuits for the Lotka-Volterra competitive neural networks. - Tetsuya Asai; Masashiro Ohtani; Hiroo Yonezu (IEEE Trans. Neural Networks, 1999)

An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. - Tetsuya Asai; Masato Koutani; Yoshihito Amemiya (IJCNN (3), 2000)

Simultaneous parametric uncertainty modeling and robust control synthesis by LFT scaling. - Tetsuya Asai; Shinji Hara; Tetsuya Iwasaki (Autom., 2000)

A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. - Yusuke Kanazawa; Takashi Yamada; Tetsuya Asai; Yoshihito Amemiya (SMC, 2002)

A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. - Tetsuya Asai; Yuusaku Nishimiya; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

An analog neural oscillator circuit for locomotion controller in quadruped walking robot. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (IJCNN, 2003)

Biomorphic Analog Devices based on Reaction-Diffusion Systems. - Tetsuya Asai; Yoshihito Amemiya (ISMVL, 2003)

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. - Yusuke Kanazawa; Tetsuya Asai; Yoshihito Amemiya (J. Robotics Mechatronics, 2003)

A subthreshold MOS neuron circuit based on the Volterra system. - Tetsuya Asai; Yusuke Kanazawa; Yoshihito Amemiya (IEEE Trans. Neural Networks, 2003)

An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (IEEE Trans. Neural Networks, 2003)

A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. - Tetsuya Asai; Yusuke Kanazawa; Tetsuya Hirose; Yoshihito Amemiya (IJCNN, 2004)

An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (ISCAS (3), 2004)

Design of an Artificial Central Pattern Generator with Feedback Controller. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (Intell. Autom. Soft Comput., 2004)

A MOS circuit for bursting neural oscillators with excitable oregonators. - Yusuke Kanazawa; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Electron. Express, 2004)

Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. - Hiroshi Matsubara; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Electron. Express, 2004)

A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. - Yusuke Kanazawa; Tetsuya Asai; Masayuki Ikebe; Yoshihito Amemiya (Int. J. Robotics Autom., 2004)

Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (J. Robotics Mechatronics, 2004)

Reaction-diffusion computers. - Andrew Adamatzky; Ben de Lacy Costello; Tetsuya Asai (Elsevier, 2005)

Analog current-mode CMOS implementation of central pattern generator for robot locomotion. - Kazuki Nakada; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IJCNN, 2005)

Noise performance of single-electron depressing synapses for neuronal synchrony detection. - Takahide Oya; Tetsuya Asai; Ryo Kagaya; Yoshihito Amemiya (IJCNN, 2005)

Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (ISCAS (3), 2005)

Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. - Takahide Oya; Tetsuya Asai; Yoshihito Amemiya; Alexandre Schmid; Yusuf Leblebici (ISCAS (3), 2005)

On the fault tolerance of a clustered single-electron neural network for differential enhancement. - Takahide Oya; Alexandre Schmid; Tetsuya Asai; Yusuf Leblebici; Yoshihito Amemiya (IEICE Electron. Express, 2005)

Ultralow-Power Current Reference Circuit with Low Temperature Dependence. - Tetsuya Hirose; Toshimasa Matsuoka; Kenji Taniguchi 001; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Electron., 2005)

Silicon Implementation of a Chemical Reaction-diffusion Processor for Computation of Voronoi Diagram. - Tetsuya Asai; Ben de Lacy Costello; Andrew Adamatzky (Int. J. Bifurc. Chaos, 2005)

Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. - Tetsuya Asai; Yusuke Kanazawa; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Unconv. Comput., 2005)

Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. - Takahide Oya; Tetsuya Asai; Takashi Fukui; Yoshihito Amemiya (Int. J. Unconv. Comput., 2005)

A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA. - Masayuki Ikebe; Tetsuya Asai (J. Robotics Mechatronics, 2005)

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. - Tetsuya Asai; Masayuki Ikebe; Tetsuya Hirose; Yoshihito Amemiya (Parallel Algorithms Appl., 2005)

Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Burst Synchronization in Two Pulse-Coupled Resonate-and-Fire Neuron Circuits. - Kazuki Nakada; Tetsuya Asai; Hatsuo Hayashi (IFIP PPAI, 2006)

Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron. - Kazuki Nakada; Jun Igarashi; Tetsuya Asai; Hatsuo Hayashi (ISCAS, 2006)

Power-supply circuits for ultralow-power subthreshold MOS-LSIs. - Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Electron. Express, 2006)

Design methodologies for compact logic circuits based on collision-based computing. - Kazuhito Yamada; Ikuko N. Motoike; Tetsuya Asai; Yoshihito Amemiya (IEICE Electron. Express, 2006)

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. - Tetsuya Asai; Taishi Kamiya; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Bifurc. Chaos, 2006)

Analog Vlsi Implementation of Resonate-and-fire Neuron. - Kazuki Nakada; Tetsuya Asai; Hatsuo Hayashi (Int. J. Neural Syst., 2006)

Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. - Gessyca Maria Tovar; Eric Shun Fukuda; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (ICONIP (2), 2007)

Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. - Gessyca Maria Tovar; Eric Shun Fukuda; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IJCNN, 2007)

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (ISCAS, 2007)

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. - Akira Utagawa; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Discrete Dynamical Systems Consisting of Single-electron Circuits. - Andrew Kilinga Kikombo; Takahide Oya; Tetsuya Asai; Yoshihito Amemiya (Int. J. Bifurc. Chaos, 2007)

Single-electron Circuits Performing Dendritic Pattern Formation with Nature-Inspired Cellular Automata. - Takahide Oya; Ikuko N. Motoike; Tetsuya Asai (Int. J. Bifurc. Chaos, 2007)

A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. - Motoyoshi Takahashi; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Bifurc. Chaos, 2007)

A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. - Kazuki Nakada; Tetsuya Asai; Tetsuya Hirose; Hatsuo Hayashi; Yoshihito Amemiya (Neurocomputing, 2007)

A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. - Takahide Oya; Tetsuya Asai; Yoshihito Amemiya (Int. J. Unconv. Comput., 2007)

Striped and Spotted Pattern Generation on Reaction-diffusion Cellular Automata - Theory and LSI Implementation. - Youhei Suzuki; Takahiro Takayama; Ikuko N. Motoike; Tetsuya Asai (Int. J. Unconv. Comput., 2007)

CMOS Smart Sensor for Monitoring the Quality of Perishables. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEEE J. Solid State Circuits, 2007)

Editorial. - Andrew Adamatzky; Christof Teuscher; Tetsuya Asai (Int. J. Parallel Emergent Distributed Syst., 2007)

Stochastic Synchronization and Array-Enhanced Coherence Resonance in a Bio-inspired Chemical Sensor Array. - Kazuki Nakada; Jun Igarashi; Tetsuya Asai; Katsumi Tateno; Hatsuo Hayashi; Yoshitaka Ohtubo; Tsutomu Miki; Kiyonori Yoshii (CSE, 2008)

A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (ESSCIRC, 2008)

Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. - Gessyca Maria Tovar; Tetsuya Asai; Yoshihito Amemiya (ICONIP (2), 2008)

Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. - Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Electron. Express, 2008)

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. - Akira Utagawa; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. - Kazuhito Yamada; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Unconv. Comput., 2008)

Nature-inspired Single-electron Computers. - Tetsuya Asai; Takahide Oya (Artificial Life Models in Hardware, 2009)

A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (ASP-DAC, 2009)

A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. - Ken Ueno; Tetsuya Asai; Yoshihito Amemiya (ESSCIRC, 2009)

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. - Tomoki Iida; Tetsuya Asai; Eiichi Sano; Yoshihito Amemiya (ICECS, 2009)

Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. - Andrew Kilinga Kikombo; Tetsuya Asai; Yoshihito Amemiya (ICONIP (2), 2009)

A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. - Andrew Kilinga Kikombo; Tetsuya Asai; Takahide Oya; Alexandre Schmid; Yusuf Leblebici; Yoshihito Amemiya (IJCNN, 2009)

On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. - Yusuke Tsugita; Ken Ueno; Tetsuya Asai; Yoshihito Amemiya; Tetsuya Hirose (ISCAS, 2009)

Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. - Ken Ueno; Tetsuya Asai; Yoshihito Amemiya (ISCAS, 2009)

Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. - Andrew Kilinga Kikombo; Tetsuya Asai; Yoshihito Amemiya (NanoNet, 2009)

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. - Taichi Ogawa; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. - Akira Utagawa; Tohru Sahashi; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. - Andrew Kilinga Kikombo; Tetsuya Asai; Takahide Oya; Alexandre Schmid; Yusuf Leblebici (Int. J. Nanotechnol. Mol. Comput., 2009)

A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEEE J. Solid State Circuits, 2009)

Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon. - Yuzuru Ohba; Masaki Sazawa; Kiyoshi Ohishi; Tetsuya Asai; Katsuyuki Majima; Yukio Yoshizawa; Koichi Kageyama (IEEE Trans. Ind. Electron., 2009)

Unconventional Computing, Novel Hardware for. - Tetsuya Asai (Encyclopedia of Complexity and Systems Science, 2009)

High performance sensor-less injection force control considering friction phenomenon. - Tetsuya Asai; Yuzuru Ohba; Kiyoshi Ohishi; Katsuyuki Majima; Shiro Urushihara; Koichi Kageyama (AMC, 2010)

Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. - Gessyca Maria Tovar; Tetsuya Asai; Yoshihito Amemiya (ICONIP (1), 2010)

A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. - Nobuo Akou; Tetsuya Asai; Takeshi Yanagida; Tomoji Kawai; Yoshihito Amemiya (IEICE Electron. Express, 2010)

High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. - Shin'ichi Asai; Ken Ueno; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Electron., 2010)

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. - Yusuke Tsugita; Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Electron., 2010)

A CMOS Phase-Shift oscillator Based on the conduction of Heat. - Takaaki Hirai; Tetsuya Asai; Yoshihito Amemiya (J. Circuits Syst. Comput., 2010)

A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. - Andrew Kilinga Kikombo; Tetsuya Asai; Yoshihito Amemiya (Int. J. Unconv. Comput., 2011)

Dynamical systems design of nonlinear oscillators using phase reduction approach. - Kazuki Nakada; Keiji Miura; Tetsuya Asai; Hisa-Aki Tanaka (APCCAS, 2012)

Silicon neuron design based on phase reduction analysis. - Kazuki Nakada; Keiji Miura; Tetsuya Asai (SCIS&ISIS, 2012)

C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. - Eric Shun Fukuda; Hideyuki Kawashima; Hiroaki Inoue; Taro Fujii; Koichiro Furuta; Tetsuya Asai; Masato Motomura (ARC, 2013)

Dynamical system design for silicon neurons using phase reduction approach. - Kazuki Nakada; Keiji Miura; Tetsuya Asai (EMBC, 2013)

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. - Katsuki Ohata; Yukitoshi Sanada; Tetsuro Ogaki; Kento Matsuyama; Takanori Ohira; Satoshi Chikuda; Masaki Igarashi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Tadahiro Kuroda (ICECS, 2013)

Exploiting hardware reconfigurability on window join. - Eric Shun Fukuda; Hideyuki Kawashima; Hiroaki Inoue; Tetsuya Asai; Masato Motomura (HPCS, 2013)

A restricted dynamically reconfigurable architecture for low power processors. - Takeshi Hirao; Dahoo Kim; Itaru Hida; Tetsuya Asai; Masato Motomura (ReConFig, 2013)

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. - Itaru Hida; Dahoo Kim; Tetsuya Asai; Masato Motomura (A-SSCC, 2014)

Signal Amplification by Circular Single-Electron Oscillator Network with Stochastic Resonance. - Hiroyuki Otake; Kazuyoshi Ishimura; Tetsuya Asai; Takahide Oya (BICT, 2014)

Caching memcached at reconfigurable network interface. - Eric Shun Fukuda; Hiroaki Inoue; Takashi Takenaka; Dahoo Kim; Tsunaki Sadahisa; Tetsuya Asai; Masato Motomura (FPL, 2014)

Achieving higher performance of memcached by caching at network interface. - Eric Shun Fukuda; Hiroaki Inoue; Takashi Takenaka; Dahoo Kim; Tsunaki Sadahisa; Tetsuya Asai; Masato Motomura (FPT, 2014)

Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. - Lizeth Gonzalez-Carabarin; Tetsuya Asai; Masato Motomura (IEICE Electron. Express, 2014)

Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. - Masayuki Ikebe; Daisuke Uchida; Yasuhiro Take; Makito Someya; Satoshi Chikuda; Kento Matsuyama; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (VLSIC, 2015)

Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. - Eric Shun Fukuda; Hiroaki Inoue; Takashi Takenaka; Dahoo Kim; Tsunaki Sadahisa; Tetsuya Asai; Masato Motomura (J. Inf. Process., 2015)

Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. - Kamal El-Sankary; Tetsuya Asai; Masato Motomura; Tadahiro Kuroda (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. - Itaru Hida; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APCCAS, 2016)

Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. - Tetsuya Asai; Masafumi Mori; Toshiyuki Itou; Yasuhiro Take; Masayuki Ikebe; Tadahiro Kuroda; Masato Motomura (ESSCIRC, 2016)

Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. - Kodai Ueyoshi; Takao Marukame; Tetsuya Asai; Masato Motomura; Alexandre Schmid (ISCAS, 2016)

An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. - Hotaka Kusano; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (ReConFig, 2016)

FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. - Kentaro Orimo; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (ReConFig, 2016)

Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. - Miho Ushida; Alexandre Schmid; Tetsuya Asai; Kazuyoshi Ishimura; Masato Motomura (Int. J. Unconv. Comput., 2016)

Accelerating deep learning by binarized hardware. - Shinya Takamaeda-Yamazaki; Kodai Ueyoshi; Kota Ando; Ryota Uematsu; Kazutoshi Hirose; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APSIPA, 2017)

An image sensor/processor 3D stacked module featuring ThruChip interfaces. - Masayuki Ikebe; Tetsuya Asai; Masafumi Mori; Toshiyuki Itou; Daisuke Uchida; Yasuhiro Take; Tadahiro Kuroda; Masato Motomura (ASP-DAC, 2017)

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. - Aoi Tanibata; Alexandre Schmid; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Masato Motomura; Tetsuya Asai (FPL, 2017)

A Time-Division Multiplexing Ising Machine on FPGAs. - Kasho Yamamoto; Weiqiang Huang; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (HEART, 2017)

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. - Kazutoshi Hirose; Ryota Uematsu; Kota Ando; Kentaro Orimo; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (CANDAR, 2017)

Exploring optimized accelerator design for binarized convolutional neural networks. - Kodai Ueyoshi; Kota Ando; Kentaro Orimo; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (IJCNN, 2017)

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. - Kodai Ueyoshi; Takao Marukame; Tetsuya Asai; Masato Motomura; Alexandre Schmid (ISCAS, 2017)

Low latency divider using ensemble of moving average curves. - Yuhan Fu; Masayuki Ikebe; Takeshi Shimada; Tetsuya Asai; Masato Motomura (ISQED, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Quantization Error-Based Regularization in Neural Networks. - Kazutoshi Hirose; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (SGAI Conf., 2017)

Special issue of emerging stochastic computing and hardware. - Takahide Oya; Tetsuya Asai (Int. J. Parallel Emergent Distributed Syst., 2017)

Noise-assisted transmission of spikes in Maeda-Makino artificial neuron arrays. - Enrico Prati; Ernesto Giussani; Giorgio Ferrari; Tetsuya Asai (Int. J. Parallel Emergent Distributed Syst., 2017)

Design and evaluation of single-electron associative memory circuit. - Makoto Takano; Tetsuya Asai; Takahide Oya (Int. J. Parallel Emergent Distributed Syst., 2017)

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. - Takao Marukame; Kodai Ueyoshi; Tetsuya Asai; Masato Motomura; Alexandre Schmid; Masamichi Suzuki; Yusuke Higashi; Yuichiro Mitani (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (FPT, 2018)

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. - Takeshi Shimada; Masayuki Ikebe; Prasoon Ambalathankandy; Shinya Takamaeda-Yamazaki; Masato Motomura; Tetsuya Asai (ICASSP, 2018)

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. - Takumi Kudo; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Ryota Uematsu; Yuka Oba; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (MCSoC, 2018)

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. - Prasoon Ambalathankandy; Takeshi Shimada; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe (VCIP, 2018)

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. - Aoi Tanibata; Alexandre Schmid; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Masato Motomura; Tetsuya Asai (Complex., 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. - Prasoon Ambalathankandy; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe; Hotaka Kusano (Microprocess. Microsystems, 2018)

Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors. - Tetsuya Asai (Handbook of Memristor Networks, 2019)

DeltaNet: Differential Binary Neural Network. - Yuka Oba; Kota Ando; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (ASAP, 2019)

Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. - Prasoon Ambalathankandy; Yafei Ou; Jyotsna Kochiyil; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe (DICTA, 2019)

A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. - Yuki Hirayama; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (CANDAR, 2019)

An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. - Tatsuya Kaneko; Hiroshi Momose; Tetsuya Asai (ReConFig, 2019)

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEICE Trans. Inf. Syst., 2019)

FPGA-Based Annealing Processor with Time-Division Multiplexing. - Kasho Yamamoto; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (IEICE Trans. Inf. Syst., 2019)

A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. - Yuki Hirayama; Tetsuya Asai; Masato Motomura; Shinya Takamaeda (Int. J. Netw. Comput., 2020)

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. - Prasoon Ambalathankandy; Masayuki Ikebe; Takayuki Yoshida; Takeshi Shimada; Shinya Takamaeda; Masato Motomura; Tetsuya Asai (IEEE Trans. Circuits Syst. Video Technol., 2020)

Performance of reservoir computing in a random network of single-walled carbon nanotubes complexed with polyoxometalate. - Megumi Akai-Kasaya; Yuki Takeshima; Shaohua Kan; Kohei Nakajima; Takahide Oya; Tetsuya Asai (Neuromorph. Comput. Eng., 2022)

Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. - Yafei Ou; Prasoon Ambalathankandy; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe (IEEE Trans. Circuits Syst. Video Technol., 2022)

Holmes: A Hardware-Oriented Optimizer Using Logarithms. - Yoshiharu Yamagishi; Tatsuya Kaneko; Megumi Akai-Kasaya; Tetsuya Asai (IEICE Trans. Inf. Syst., 2022)

Edge AI Online Training Architecture Using Multi-Phase-Quantization Optimizer. - Itsuki Akeno; Hiiro Yamazaki; Tetsuya Asai; Kota Ando (IJCNN, 2024)

Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference. - Koki Minagawa; Taisei Saito; Sena Kojima; Kota Ando; Tetsuya Asai (IJCNN, 2024)

Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights. - Taisei Saito; Kota Ando; Tetsuya Asai (IEICE Trans. Inf. Syst., 2024)

SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA. - Yuki Abe; Kohei Nishida; Kota Ando; Tetsuya Asai (Int. J. Parallel Emergent Distributed Syst., 2024)