MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing. - Robert H. Halstead Jr.; Tetsuya Fujita (ISCA, 1988)

Substrate noise influence on circuit performance in variable threshold-voltage scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Toshiaki Mori; Kenji Matsuo; Masakazu Kakumu; Takayasu Sakurai (ISLPED, 1996)

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakurnu; et al. (IEEE J. Solid State Circuits, 1996)

Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. - Tadahiro Kuroda; Tetsuya Fujita; Makato Noda; Yasushi Itabashi; Satohiko Kabumoto; T. S. Wong; Dave Beeson; Dave Gray (IEEE J. Solid State Circuits, 1996)

Variable supply-voltage scheme for low-power high-speed CMOS digital design. - Tadahiro Kuroda; Kojiro Suzuki; Shinji Mita; Tetsuya Fujita; Fumiyuki Yamane; Fumihiko Sano; Akihiko Chiba; Yoshinori Watanabe; Koji Matsuda; Takeo Maeda; Takayasu Sakurai; Tohru Furuyama (IEEE J. Solid State Circuits, 1998)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. - Masafumi Takahashi; Mototsugu Hamada; Tsuyoshi Nishikawa; Hideho Arakida; Tetsuya Fujita; Fumitoshi Hatori; Shinji Mita; Kojiro Suzuki; Akihiko Chiba; Toshihiro Terazawa; Fumihiko Sano; Yoshinori Watanabe; et al. (IEEE J. Solid State Circuits, 1998)

A single-chip 802.11a MAC/PHY with a 32-b RISC processor. - Toshio Fujisawa; Jun Hasegawa; Koji Tsuchie; Tatsuo Shiozawa; Tetsuya Fujita; Toshitada Saito; Yasuo Unekawa (IEEE J. Solid State Circuits, 2003)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. - Chen Kong Teh; Mototsugu Hamada; Tetsuya Fujita; Hiroyuki Hara; N. Ikumi; Yukihito Oowaki (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

Learning of situation dependent prediction toward acquiring physical causality. - Masaki Ogino; Tetsuya Fujita; Sawa Fuke; Minoru Asada (EpiRob, 2009)

A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications. - Tatsuya Mori; Yasuyuki Ueda; Nobuhiro Nonogaki; Toshihiro Terazawa; Milosz Sroka; Tetsuya Fujita; Takeshi Kodaka; Takayuki Mori; Kumiko Morita; Hideho Arakida; Takashi Miura; Yuji Okuda; et al. (IEEE J. Solid State Circuits, 2009)

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Takayoshi Shimazawa; Yasuo Ohara; Takashi Miyamori; et al. (ISSCC, 2010)

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. - Daisuke Taki; Tatsuo Shiozawa; Kuniaki Ito; Youichiro Shiba; Kouji Horisaki; Hirotsugu Kajihara; Toshiyuki Yamagishi; Masahiro Sekiya; Akira Yamaga; Tetsuya Fujita; Hiroyuki Hara; Masanori Kuwahara; et al. (COOL Chips, 2011)

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. - Chen Kong Teh; Tetsuya Fujita; Hiroyuki Hara; Mototsugu Hamada (ISSCC, 2011)

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Masatoshi Fukuda; Yasuhiro Koshio; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Hirokazu Ezawa; et al. (IEEE J. Solid State Circuits, 2011)

Improvement of Factor Model with Text Information Based on Factor Model Construction Process. - Ryosuke Saga; Tetsuya Fujita; Kodai Kitami; Kazunori Matsumoto (IIMSS, 2013)