Hardware Evaluation of the AES Finalists. - Tetsuya Ichikawa; Tomomi Kasuya; Mitsuru Matsui (AES Candidate Conference, 2000)

Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms - Design and Analysis. - Kazumaro Aoki; Tetsuya Ichikawa; Masayuki Kanda; Mitsuru Matsui; Shiho Moriai; Junko Nakajima; Toshio Tokita (Selected Areas in Cryptography, 2000)

The 128-Bit Block Cipher Camellia. - Kazumaro Aoki; Tetsuya Ichikawa; Masayuki Kanda; Mitsuru Matsui; Shiho Moriai; Junko Nakajima; Toshio Tokita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Random Switching Logic: A Countermeasure against DPA based on Transition Probability. - Daisuke Suzuki; Minoru Saeki; Tetsuya Ichikawa (IACR Cryptol. ePrint Arch., 2004)

DPA Leakage Models for CMOS Logic Circuits. - Daisuke Suzuki; Minoru Saeki; Tetsuya Ichikawa (CHES, 2005)

Leakage Analysis of DPA Countermeasures at the Logic Level. - Minoru Saeki; Daisuke Suzuki; Tetsuya Ichikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. - Daisuke Suzuki; Minoru Saeki; Tetsuya Ichikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)