A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Katsuhiko Sato; Tsukasa Shirotori; Masakazu Kakuma; Shigeru Morita; Masaaki Kinugawa; Tetsuya Asami; Kazuhito Narita; Jun-Ichi Matsunaga; Akira Higuchi; et al. (IEEE J. Solid State Circuits, 1988)

A 32 kbyte integrated cache memory. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Tsukasa Shirotori; Toshinari Takayanagi; Tetsuya Iizuka; Takeo Maeda; Jinichi Matsunaga; Hiromichi Fuji; Kenji Maeguchi; Kiyoshi Kobayashi; Tomoyuki Ando; et al. (IEEE J. Solid State Circuits, 1989)

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. - Kazutaka Nogami; Takayasu Sakurai; Kazuhiro Sawada; Kenji Sakaue; Yuichi Miyazawa; Shinichi Tanaka; Ypocjo Hiruta; Katsuto Katoh; Toshinari Takayanagi; Tsukasa Shirotori; Yasuo Itoh; Masanori Uchida; et al. (IEEE J. Solid State Circuits, 1990)

Automatic Visualization Method for Visual Data Mining. - Yuichi Iizuka; Hisako Shiohara; Tetsuya Iizuka; Seiji Isobe (PAKDD, 1998)

Mining sequential patterns including time intervals. - Mariko Yoshida; Tetsuya Iizuka; Hisako Shiohara; Masanori Ishiguro (Data Mining and Knowledge Discovery: Theory, Tools, and Technology, 2000)

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2004)

Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISQED, 2004)

Exact minimum-width transistor placement without dual constraint for CMOS cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ACM Great Lakes Symposium on VLSI, 2005)

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Timing-driven cell layout de-compaction for yield optimization by critical area minimization. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (DATE, 2006)

Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ICECS, 2006)

Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISCAS, 2006)

Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. - Kenichiro Kurihara; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ICECS, 2007)

OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISQED, 2007)

Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. - Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (DDECS, 2010)

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. - Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2010)

Time-to-digital converter based on time difference amplifier with non-linearity calibration. - Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2010)

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. - Jaehyun Jeong; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2011)

An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. - Tetsuya Iizuka; Kunihiro Asada (DDECS, 2011)

A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. - Kazutoshi Kodama; Tetsuya Iizuka; Kunihiro Asada (ESSCIRC, 2011)

All-digital ramp waveform generator for two-step single-slope ADC. - Tetsuya Iizuka; Kunihiro Asada (IEICE Electron. Express, 2011)

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. - Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. - Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Cascaded Time Difference Amplifier with Differential Logic Delay Cell. - Shingo Mandai; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (J. Next Gener. Inf. Technol., 2011)

Impact of All-Digital PLL on SoC Testing. - Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (Asian Test Symposium, 2012)

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. - Toru Nakura; Yoshio Mita; Tetsuya Iizuka; Kunihiro Asada (CICC, 2012)

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. - Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2012)

A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. - Tetsuya Iizuka; Satoshi Miura; Ryota Yamamoto; Yutaka Chiba; Shunichi Kubo; Kunihiro Asada (IEICE Trans. Electron., 2012)

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. - Kazutoshi Kodama; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2012)

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. - Rimon Ikeno; Takashi Maruyama; Tetsuya Iizuka; Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2013)

A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. - Tetsuya Iizuka; Satoshi Miura; Yohei Ishizone; Yoshimichi Murakami; Kunihiro Asada (CICC, 2013)

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. - Tetsuya Iizuka; Teruki Someya; Toru Nakura; Kunihiro Asada (CICC, 2013)

A Pulse Width controlled PLL and its automated design flow. - Norihito Tohge; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2013)

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISPD, 2013)

Session 26 overview: High-speed data converters. - Boris Murmann; Tetsuya Iizuka (ISSCC, 2013)

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. - Manoj Sachdev; Tetsuya Iizuka (CICC, 2014)

High-resolution measurement of magnetic field generated from cryptographic LSIs. - Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Akihiko Sasaki; Makoto Yamada; Osamu Morita; Kunihiro Asada (SAS, 2014)

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. - Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (A-SSCC, 2015)

Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects. - Robert C. Aitken; Tetsuya Iizuka (CICC, 2015)

Session 3 - Optical interconnect and reliability enhancement techniques. - Tetsuya Iizuka; Takahiro J. Yamaguchi (CICC, 2015)

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (DDECS, 2015)

F1: High-speed interleaved ADCs. - Stephane Le Tuai; Borivoje Nikolic; Tetsuya Iizuka; Ichiro Fujimori (ISSCC, 2015)

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. - Takashi Toi; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (NORCAS, 2015)

A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. - Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Akihiko Sasaki; Makoto Yamada; Osamu Morita; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2015)

A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. - Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada (A-SSCC, 2016)

Analytical design optimization of sub-ranging ADC based on stochastic comparator. - Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (DATE, 2016)

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. - Tetsuya Iizuka; Norihito Tohge; Satoshi Miura; Yoshimichi Murakami; Toru Nakura; Kunihiro Asada (ESSCIRC, 2016)

Resonant power supply noise reduction using a triangular active charge injection. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2016)

Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. - Nguyen Ngoc Mai Khanh; Rimon Ikeno; Takahiro J. Yamaguchi; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2016)

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. - Toru Nakura; Naoki Terao; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ITC, 2016)

An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (J. Circuits Syst. Comput., 2016)

FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path. - Tetsuya Iizuka; Asad A. Abidi (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance. - Tetsuya Iizuka; Asad A. Abidi (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

CMOS-on-quartz pulse generator for low power applications. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ASP-DAC, 2017)

A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ASP-DAC, 2017)

Session 4 - Modeling and measurement of mixed-signal circuits. - Colin McAndrew; Tetsuya Iizuka (CICC, 2017)

High Spatial Resolution Detection Method for Point Light Source in Scintillator. - Kai Xu; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (Computational Imaging, 2017)

Extension of power supply impedance emulation method on ATE for multiple power domain. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ETS, 2017)

An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. - Ryuichi Enomoto; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ICECS, 2017)

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. - Takaaki Ito; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ICECS, 2017)

A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2017)

A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. - Xiao Yang; Kai Xu; Tetsuya Iizuka; Toru Nakura; Hongbo Zhu; Kunihiro Asada (IEEE SENSORS, 2017)

Impulse signal generator based on current-mode excitation and transmission line resonator. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (NEWCAS, 2017)

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A PLL Compiler from Specification to GDSII. - Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. - Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2017)

A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Rimon Ikeno; Takahiro J. Yamaguchi; Tetsuya Iizuka; Kunihiro Asada (MWSCAS, 2018)

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC, 2018)

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC (Selected Papers), 2018)

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (J. Electron. Test., 2018)

Time-domain approach for analog circuits in deep sub-micron LSI. - Kunihiro Asada; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda (IEICE Electron. Express, 2018)

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. - Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit. - Tetsuya Iizuka; Asad A. Abidi (IEICE Trans. Electron., 2018)

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2018)

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. - Toru Nakura; Tsukasa Kagaya; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2018)

Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit. - Tetsuya Iizuka; Takaaki Ito; Asad A. Abidi (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. - Nguyen Ngoc Mai Khanh; Shigeru Nakajima; Tetsuya Iizuka; Yoshio Mita; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2018)

A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. - Naoki Ojima; Zule Xu; Tetsuya Iizuka (NEWCAS, 2019)

Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. - Tetsuya Iizuka; Kai Xu; Xiao Yang; Toru Nakura; Kunihiro Asada (IEICE Electron. Express, 2019)

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. - Wang Jing; Tetsuya Iizuka; Zule Xu; Toru Nakura (IEICE Electron. Express, 2019)

A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS. - Yoshitaka Otsuki; Daisuke Yamazaki; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka (IEICE Electron. Express, 2019)

Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. - Daigo Takahashi; Tetsuya Iizuka; Nguyen Ngoc Mai Khanh; Toru Nakura; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2019)

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. - Ryuichi Enomoto; Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. - Zolboo Byambadorj; Koji Asami; Takahiro J. Yamaguchi; Akio Higo; Masahiro Fujita; Tetsuya Iizuka (ATS, 2020)

A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. - Masaru Osada; Zule Xu; Tetsuya Iizuka (VLSI Circuits, 2020)

11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS. - Daisuke Yamazaki; Yoshitaka Otsuki; Takafumi Hara; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka (IET Circuits Devices Syst., 2020)

Theoretical Analysis of Noise Figure for Modulated Wideband Converter. - Zolboo Byambadorj; Koji Asami; Takahiro J. Yamaguchi; Akio Higo; Masahiro Fujita; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. - Zolboo Byambadorj; Koji Asami; Takahiro J. Yamaguchi; Akio Higo; Masahiro Fujita; Tetsuya Iizuka (IEEE Trans. Circuits Syst., 2020)

A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. - Tetsuya Iizuka; Hao Xu 005; Asad A. Abidi (ESSCIRC, 2021)

Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. - Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Kunihiro Asada (ICICDT, 2021)

A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. - Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Circuits, 2021)

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. - Zule Xu; Naoki Ojima; Shuowei Li; Tetsuya Iizuka (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. - Masaru Osada; Zule Xu; Tetsuya Iizuka (ESSCIRC, 2022)

140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS. - Nguyen Ngoc Mai Khanh; Daisuke Yamazaki; Tetsuya Iizuka (ICICDT, 2022)

A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. - Ryoya Shibata; Zule Xu; Yasushi Hotta; Hitoshi Tabata; Tetsuya Iizuka (ISCAS, 2022)

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. - Zunsong Yang; Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Technology and Circuits, 2022)

CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks. - Xiangyu Chen; Takeaki Yajima; Hisashi Inoue; Isao H. Inoue; Zolboo Byambadorj; Tetsuya Iizuka (CoRR, 2022)

High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. - Zolboo Byambadorj; Koji Asami; Takahiro J. Yamaguchi; Akio Higo; Masahiro Fujita; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. - Masaru Osada; Zule Xu; Ryoya Shibata; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers. - Akira Matsuoka; Tomohiro Nezuka; Tetsuya Iizuka (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. - Tetsuya Iizuka; Meikan Chin; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2022)

Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit. - Zhenyu Cheng 003; Zunsong Yang; Yuyang Zhu; Md Shamim Sarker; Hiroyasu Yamahara; Munetoshi Seki; Hitoshi Tabata; Tetsuya Iizuka (ICICDT, 2023)

Dynamic Circuit Characterization and a Single Ring-Oscillator-Based Test Structure for Its Timing Parameter Extraction. - Haoming Zhang; Shuowei Li; Tetsuya Iizuka (ICICDT, 2023)

A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit. - Yuyang Zhu; Zunsong Yang; Zhenyu Cheng 003; Md Shamim Sarker; Hiroyasu Yamahara; Munetoshi Seki; Hitoshi Tabata; Tetsuya Iizuka (ICICDT, 2023)

INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications. - Haoyuan Gao; Hao Xu; Xinyi Lin; Yan Liu; Zhidong Tang; Xufeng Kou; Xingyu Zhang; Tetsuya Iizuka; Na Yan (ICTA, 2023)

Long-time-constant leaky-integrating oxygen-vacancy drift-diffusion FET for human-interactive spiking reservoir computing. - Hisashi Inoue; Hiroto Tamura; Ai Kitoh; Xiangyu Chen; Zolboo Byambadorj; Takeaki Yajima; Yasushi Hotta; Tetsuya Iizuka; Gouhei Tanaka; Isao H. Inoue (VLSI Technology and Circuits, 2023)

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. - Zunsong Yang; Masaru Osada; Shuowei Li; Yuyang Zhu; Tetsuya Iizuka (VLSI Technology and Circuits, 2023)

A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation. - Akira Matsuoka; Yo Kumano; Tomohiro Nezuka; Yoshikazu Furuta; Tetsuya Iizuka (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Analysis of SAR ADC Performance Enhancement Utilizing Stochastic Resonance. - Ryoya Shibata; Yasushi Hotta; Hitoshi Tabata; Tetsuya Iizuka (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Khai-Duy Nguyen; Tetsuya Iizuka; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2024)

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. - Tianle Chen; Hongyu Ren; Zunsong Yang; Yunbo Huang; Xianghe Meng; Weiwei Yan; Weidong Zhang; Xuqiang Zheng; Xuan Guo; Tetsuya Iizuka; Pui-In Mak; Yong Chen 005; et al. (VLSI Technology and Circuits, 2024)

Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons. - Nanako Kimura; Ckristian Duran; Zolboo Byambadorj; Ryosho Nakane; Tetsuya Iizuka (CoRR, 2024)

150GHz Fundamental Oscillator Utilizing Transmission-Line-Based Inter-Stage Matching in 130nm SiGe BiCMOS Technology. - Sota Kano; Tetsuya Iizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. - Yuyang Zhu; Zunsong Yang; Masaru Osada; Haoming Zhang; Tetsuya Iizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit. - Haoming Zhang; Shuowei Li; Tetsuya Iizuka (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. - Masaru Osada; Zule Xu; Zunsong Yang; Tetsuya Iizuka (IEEE J. Solid State Circuits, 2024)

Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC). - Ken Takeuchi; Tetsuya Iizuka; Kazuko Nishimura; Jerald Yoo (IEEE J. Solid State Circuits, 2024)

Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes. - Sota Kano; Naoto Usami; Atsushi Tomiki; Tetsuya Iizuka (ASP-DAC, 2025)

Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection. - Yuyang Zhu; Zunsong Yang; Zhenyu Cheng 003; Md Shamim Sarker; Hiroyasu Yamahara; Munetoshi Seki; Hitoshi Tabata; Tetsuya Iizuka (ASP-DAC, 2025)

A 172.1dB-FoM 19.5kHz-BW DT ΔΣ ADC Using CLS-Assisted Fast Self-Quenching Floating Inverter Amplifier with Sampling Noise Cancellation. - Ximing Wang; Yo Kumano; Tomohiro Nezuka; Yoshikazu Furuta; Tetsuya Iizuka (ISCAS, 2025)

A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation. - Haoming Zhang; Yuyang Zhu; Masaru Osada; Tetsuya Iizuka (ISSCC, 2025)

Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework. - Shuowei Li; Ckristian Duran; Ritaro Takenaka; Tetsuya Iizuka (IEEE Access, 2025)

Analysis of Intrinsic Quantizer Non-Linearity in ΔΣ ADCs. - Yo Kumano; Tetsuya Iizuka (IEICE Trans. Electron., 2025)

An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC. - Shuowei Li; Zunsong Yang; Tetsuya Iizuka (Circuits Syst. Signal Process., 2025)

A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation. - Haoming Zhang; Masaru Osada; Yuyang Zhu; Tetsuya Iizuka (IEEE J. Solid State Circuits, 2025)

Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs. - Yuyang Zhu; Masaru Osada; Haoming Zhang; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)