A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. - Yuichiro Murachi; Kosuke Mizuno; Junichi Miyakoshi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2008)

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (FPL, 2010)

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Tsuyoshi Fujinaga; Shintaro Izumi; Yasuo Ariki; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2011)