A 24-b 50-ns digital image signal processor. - Shin-ichi Nakagawa; Hideyuki Terane; Tetsuya Matsumura; Hiroshi Segawa; Masahiko Yoshimoto; Hirofumi Shinohara; Shuichi Kato; Masahiro Hatanaka; Hideo Ohira; Yoshiaki Kato; Mamoru Iwatsuki; Kinya Tabuchi; et al. (IEEE J. Solid State Circuits, 1990)

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. - Atsuo Hanami; Stefan Scotzniovsky; Kazuya Ishihara; Tetsuya Matsumura; Shin'ichi Takeuchi; Haruyuki Ohkuma; Koji Nishigaki; Hirokazu Suzuki; Masahiro Kazayama; Toyohiko Yoshida; Koji Tsuchihashi (CICC, 1998)

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. - Satoshi Kumaki; Tetsuya Matsumura; Kamya Ishihara; Hiroshi Segawa; Kiyofumi Kawamoto; Hideo Ohira; Toshiaki Shimada; Hidenori Sato; Takashi Hattori; Tetsuro Wada; Hiroshi Honma; Tetsuya Watanabe; et al. (CICC, 1999)

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shin-ichi Hattori; et al. (IEEE J. Solid State Circuits, 2002)

Obstacle Avoidance with Simultaneous Translational and Rotational Motion Control for Autonomous Mobile Robot. - Masaki Takahashi; Takafumi Suzuki; Tetsuya Matsumura; Ayanori Yorozu (ICINCO (2), 2011)

Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot Considering Shape of the Robot and Movable Area by Heights. - Ayanori Yorozu; Takafumi Suzuki; Tetsuya Matsumura; Masaki Takahashi (IAS (1), 2012)

Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot - 2nd Report: Robot Model Considering Moving Parts and Evaluation of Movable Area by Heights. - Ayanori Yorozu; Takafumi Suzuki; Tetsuya Matsumura; Masaki Takahashi (ICINCO (2), 2012)

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Yuichiro Ishii; Tetsuya Matsumura; Yoshio Matsuda (ISQED, 2013)

The LSI implementation of a memory based field programmable device for MCU peripherals. - Tetsuya Matsumura; Naoya Okada; Yoshifumi Kawamura; Koji Nii; Kazutami Arimoto; Hiroshi Makino; Yoshio Matsuda (DDECS, 2014)

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Makoto Yabuuchi; Kazuyoshi Okamoto; Yasumasa Tsukamoto; Shinji Tanaka; Koji Tanaka; Tetsuya Matsumura; Kazutaka Mori; Kazumasa Yanagisawa (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm. - Tetsuya Matsumura; Aoi Kurokawa; Kousuke Imamura; Yoshio Matsuda (DDECS, 2015)

Human-centered X-Y-T-space path planning for mobile robot in dynamic environments. - Ippei Nishitani; Tetsuya Matsumura; Mayumi Ozawa; Ayanori Yorozu; Masaki Takahashi (Robotics Auton. Syst., 2015)

Automatic rule registration and deletion function on a packet lookup engine LSI. - Tetsuya Matsumura; Kousuke Imamura; Yoshifumi Kawamura; Yoshio Matsuda (ISPACS, 2016)

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. - Yoshifumi Kawamura; Naoya Okada; Yoshio Matsuda; Tetsuya Matsumura; Hiroshi Makino; Kazutami Arimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Design for three-dimensional sound processor using high-level synthesis. - Saya Ohira; Tetsuya Matsumura (DDECS, 2017)

A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. - Kousuke Imamura; Ryota Honda; Yoshifumi Kawamura; Naoki Miura; Masami Urano; Satoshi Shigematsu; Tetsuya Matsumura; Yoshio Matsuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor. - Yu Suzuki; Masato Ito; Satoshi Kanda; Kousuke Imamura; Yoshio Matsuda; Tetsuya Matsumura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. - Seiji Mochizuki; Kousuke Imamura; Kaito Mori; Yoshio Matsuda; Tetsuya Matsumura (IOTAIS, 2018)

Automatic Design Environment using High-level Synthesis for Reconfigurable 3D Sound Processor. - Saya Ohira; Naoki Tsuchiya; Tetsuya Matsumura (ISPACS, 2018)

Scalable Architecture for High-Resolution Real-time Optical Flow Processor. - Kousuke Imamura; Satoshi Kanda; Saya Ohira; Yoshio Matsuda; Tetsuya Matsumura (IoTaIS, 2019)

Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. - Kosuke Fukava; Kaito Mori; Kousuke Imamura; Yoshio Matsuda; Tetsuya Matsumura; Seiji Mochizuki (ISPACS, 2019)

Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis. - Saya Ohira; Naoki Tsuchiya; Tetsuya Matsumura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Implementation of Deep Learning-based Hierarchical Object Detection System for High-Resolution Images. - Makoto Sugaya; Yusei Horikawa; Kazuma Mashiko; Tomoya Minagawa; Tetsuya Matsumura (GCCE, 2022)

Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System. - Yusei Horikawa; Renpei Yoshida; Seiji Mochizuki; Tetsuya Matsumura (GCCE, 2023)

Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video. - Mai Yamaguchi; Mai Yamakawa; Seiji Mochizuki; Kousuke Imamura; Toshiki Kanamoto; Tetsuya Matsumura (GCCE, 2023)

CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images. - Yusei Horikawa; Seiji Mochizuki; Kousuke Imamura; Tetsuya Matsumura (IoTaIS, 2023)

20-µs Low-latency Simple Video Coding with High Compression Ratio for IoT Video-transmission. - Mai Yamakawa; Seiji Mochizuki; Yu Kuwahara; Tsuyoshi Kato; Kousuke Imamura; Tetsuya Matsumura (ICNC, 2025)