A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS. - Seiji Mochizuki; Tetsuya Shibayama; Masaru Hase; Fumitaka Izuhara; Kazushi Akie; Masaki Nobori; Ren Imaoka; Hiroshi Ueda; Kazuyuki Ishikawa; Hiromi Watanabe (IEEE J. Solid State Circuits, 2008)

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. - Kenichi Iwata; Seiji Mochizuki; Motoki Kimura; Tetsuya Shibayama; Fumitaka Izuhara; Hiroshi Ueda; Koji Hosogi; Hiroaki Nakata; Masakazu Ehama; Toru Kengaku; Takuichiro Nakazawa; Hiromi Watanabe (IEEE J. Solid State Circuits, 2009)

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. - Seiji Mochizuki; Katsushige Matsubara; Keisuke Matsumoto; Chi Lan Phuong Nguyen; Tetsuya Shibayama; Kenichi Iwata; Katsuya Mizumoto; Takahiro Irita; Hirotaka Hara; Toshihiro Hattori (ISSCC, 2016)

A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. - Seiji Mochizuki; Katsushige Matsubara; Keisuke Matsumoto; Chi Lan Phuong Nguyen; Tetsuya Shibayama; Kenichi Iwata; Katsuya Mizumoto; Takahiro Irita; Hirotaka Hara; Toshihiro Hattori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)