Region-based reconstruction of an indoor scene using an integration of active and passive sensing techniques. - Junichi Hoshino; Tetsuya Uemura; Isao Masuda (ICCV, 1990)

3D facial image analysis for human identification. - Takashi Nagamine; Tetsuya Uemura; Isao Masuda (ICPR (1), 1992)

Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits . - Toshio Baba; Tetsuya Uemura (ISMVL, 1997)

Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits. - Toshio Baba; Tetsuya Uemura (ISMVL, 1998)

Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. - Tetsuya Uemura; Pinaki Mazumder (Great Lakes Symposium on VLSI, 1999)

Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. - Tetsuya Uemura; Toshio Baba (ISMVL, 2000)

A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors. - Tetsuya Uemura; Toshio Baba (ISMVL, 2001)

Rise time analysis of MOBILE circuit. - Tetsuya Uemura; Pinaki Mazumder (ISCAS (5), 2002)

Proposal of Four-Valued MRAM based on MTJ/RTD Structure. - Tetsuya Uemura; Masafumi Yamamoto (ISMVL, 2003)

Four-Valued Magnetic Random Access Memory Based on Magneto Tunnel Junction and Resonant Tunneling Diode. - Tetsuya Uemura; Masafumi Yamamoto (J. Multiple Valued Log. Soft Comput., 2005)

Clinical support system using information aggregation and visualization for order data. - Shuichi Toyoda; Noboru Niki; Tetsuya Uemura; Hiromu Nishitani (Syst. Comput. Jpn., 2005)

Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. - Tetsuya Uemura; Takao Marukame; Ken-ichi Matsuda; Masafumi Yamamoto (ISMVL, 2007)