An algorithm for speech parameter generation from continuous mixture HMMs with dynamic features. - Keiichi Tokuda; Takashi Masuko; Tetsuya Yamada; Takao Kobayashi; Satoshi Imai (EUROSPEECH, 1995)

On the Computational Power of Binary Decision Diagram with Redundant Variables. - Tetsuya Yamada; Hiroto Yasuura (Formal Methods Syst. Des., 1996)

Application of phased-array antenna technology to the 21 GHz broadcasting satellite for rain-attenuation compensation. - Yutaka Kawaguchi; Hitoshi Nakagawa; Shoji Tanaka; Tetsuya Yamada (ICC, 2002)

Low-Power Design of 90-nm SuperH Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (ICCD, 2005)

A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. - Masafumi Onouchi; Tetsuya Yamada; Kimihiro Morikawa; Isamu Mochizuki; Hidetoshi Sekine (ASP-DAC, 2006)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (IEICE Trans. Electron., 2006)

Development of processor cores for digital consumer appliances. - Fumio Arakawa; Tetsuya Yamada; Takashi Okada; Makoto Ishikawa; Yuki Kondo; Motokazu Ozawa; Tomoyuki Kodama; Osamu Nishii; Toshihiro Hattori; Tatsuya Kamei; Junichi Nishimoto; Shinichi Yoshioka (Syst. Comput. Jpn., 2006)

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. - Makoto Saen; Kenichi Osada; Satoshi Misaka; Tetsuya Yamada; Yoshitaka Tsujimoto; Yuki Kondo; Tatsuya Kamei; Yutaka Yoshida; Ei Nagahama; Yusuke Nitta; Takayasu Ito; Tadashi Kameyama; et al. (ISSCC, 2007)

A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core. - Tetsuya Yamada; Naohiko Irie; Takanobu Tsunoda; Takahiro Irita; Kenji Kitagawa; Ryohei Yoshida; Keisuke Toyama 003; Motoaki Satoyama (IEICE Trans. Electron., 2007)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

Search for Alternatives and Collaboration with Incumbents: Two-Sided Sourcing Behavior in Business Markets. - Stephen Keysuk Kim; Tetsuya Yamada; Hyunchul Kim (Decis. Sci., 2008)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Beacon Tracking System and Its Performance in Search Operation for Hayabusa Sample Return Capsule. - Takahide Mizuno; Kousuke Kawahara; Kazuhiko Yamada; Yukio Kamata; Tetsuya Yamada; Hitoshi Kuninaka (IEICE Trans. Commun., 2011)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)

Battery-Aware IT Control Method for Effective Battery Use During Power Outage. - Tetsuya Yamada; Tadayuki Matsumura (GreenCom, 2012)

IT-Cooling Collaborative Control Methods for Battery-Aware IT-Systems Targeting India. - Tadayuki Matsumura; Tetsuya Yamada (ICT-GLOW, 2012)

Hardware support for resource partitioning in real-time embedded systems. - Tetsuro Honmura; Yuki Kondo; Tetsuya Yamada; Masashi Takada; Takumi Nitoh; Tohru Nojiri; Keisuke Toyama 003; Yasuhiko Saitoh; Hirofumi Nishi; Mikiko Sato; Mitaro Namiki (COOL Chips, 2013)

Artificial cell membrane system for odorant sensor: development of solution exchange driven by superabsorbent polymer for repeatable detection. - Tetsuya Yamada; Koki Kamiya; Toshihisa Osaki; Shoji Takeuchi (ISOEN, 2019)

Quantitative signal analysis of a ligand-gated ion channel on a lipid bilayer using continuous-time wavelet transformation. - Hirotaka Sugiura; Tetsuya Yamada; Atsufumi Ozoe; Yuki Kodama; Yasuhiko Takahashi; Toshihisa Osaki; Shoji Takeuchi (MHS, 2019)

Dielecrophoretic introduction of the membrane proteins into the BLM platforms for the electrophygiological analysis systems. - Hirotaka Sugiura; Toshihisa Osaki; Hisatoshi Mimura; Tetsuya Yamada; Shoji Takeuchi (IROS, 2020)

Boundedness of solutions to a parabolic attraction-repulsion chemotaxis system in R2: The attractive dominant case. - Toshitaka Nagai; Yukihiro Seki; Tetsuya Yamada (Appl. Math. Lett., 2021)

Finishing Speed Improvement Using Side Cover Plates in Gyro Finishing. - Yohei Hashimoto; Yugo Nakayama; Tatsuaki Furumoto; Akihito Sekiya; Tetsuya Yamada; Tatsuki Kawahara; Akira Hosokawa (Int. J. Autom. Technol., 2023)