Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. - Chih-Cheng Chang; Pin-Chun Chen; Teyuh Chou; I-Ting Wang; Boris Hudec; Che-Chia Chang; Chia-Ming Tsai; Tian-Sheuan Chang; Tuo-Hung Hou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

An Sram-Based Accelerator for Solving Partial Differential Equations. - Thomas Chen 003; Jacob Botimer; Teyuh Chou; Zhengya Zhang (CICC, 2019)

CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. - Teyuh Chou; Wei Tang 010; Jacob Botimer; Zhengya Zhang (MICRO, 2019)

A 1.87-mm2 56.9-GOPS Accelerator for Solving Partial Differential Equations. - Thomas Chen 003; Jacob Botimer; Teyuh Chou; Zhengya Zhang (IEEE J. Solid State Circuits, 2020)

NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. - Teyuh Chou; Wei Tang 010; Mihai D. Rotaru; Chester Liu; Rahul Dutta; Sharon Lim Pei Siang; David Ho Soon Wee; Surya Bhattacharya; Zhengya Zhang (VLSI Technology and Circuits, 2022)

AR-PIM: An Adaptive-Range Processing-in-Memory Architecture. - Teyuh Chou; Fernando García-Redondo; Paul N. Whatmough; Zhengya Zhang (ISLPED, 2023)

Load and MLP-Aware Thread Orchestration for Recommendation Systems Inference on CPUs. - Rishabh Jain; Teyuh Chou; Onur Kayiran; John Kalamatianos; Gabriel H. Loh; Mahmut T. Kandemir; Chita R. Das (ASPLOS (2), 2025)