Tracking Data Flow at Gate-Level through Structural Checking. - Thao Le 001; Jia Di; Mark Tehranipoor; Domenic Forte; Lei Wang 003 (ACM Great Lakes Symposium on VLSI, 2016)

Golden reference matching for gate-level netlist functionality identification. - Thao Le 001; Jia Di (MWSCAS, 2017)

Recent Advances in Low Power Asynchronous Circuit Design. - Jia Di; Brent A. Bell; William Bouillon; John Brady; Thao Le 001; Chien-Wei Lo; Liang Men; Spencer Nelson; Francis Sabado; Andrew Suchanek (J. Low Power Electron., 2017)

Hardware Trojan Detection and Functionality Determination for Soft IPs. - Thao Le 001; Lucas Weaver; Jia Di; Shaojie Zhang 001; Yier Jin (IVSW, 2018)

The Old Frontier of Reverse Engineering: Netlist Partitioning. - Travis Meade; Kaveh Shamsi; Thao Le 001; Jia Di; Shaojie Zhang 001; Yier Jin (J. Hardw. Syst. Secur., 2018)

Hardware IP Classification through Weighted Characteristics. - Brendan McGeehan; Flora Smith; Thao Le 001; Hunter Nauman; Jia Di (HPEC, 2019)