An Accurate Probalistic Model for Error Detection. - Thara Rejimon; Sanjukta Bhanja (VLSI Design, 2005)

Wide Limited Switch Dynamic Logic Circuit Implementations. - Thara Rejimon; Sanjukta Bhanja (VLSI Design, 2006)

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. - Thara Rejimon; Sanjukta Bhanja (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Reliability-centric probabilistic analysis of VLSI circuits. - Thara Rejimon (2006)

Probabilistic Error Modeling for Nano-Domain Logic Circuits. - Thara Rejimon; Karthikeyan Lingasubramanian; Sanjukta Bhanja (IEEE Trans. Very Large Scale Integr. Syst., 2009)