A Procedure for Selecting Diagnostic Tests. - Theo Jay Powell (IEEE Trans. Computers, 1969)

A Module Diagnostic Procedure for Combinational Logic - Theo Jay Powell (1969)

Analysis and Simulation of Parallel Signature Analyzers. - Thirumalai Sridhar; D. S. Ho; Theo J. Powell; Satish M. Thatte (ITC, 1982)

An Architecture for Testable VLSI Processors. - Satish M. Thatte; D. S. Ho; H.-T. Yuan; Thirumalai Sridhar; Theo J. Powell (ITC, 1982)

Testability Features in the TMS370 Family of Microcomputers. - Theo J. Powell; Fred Hwang; Bill Johnson (ITC, 1988)

Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]. - Theo J. Powell; Kenneth M. Butler; Mike Ales; Roy Haley; Mark Perry (VTS, 1994)

Test Generation and Design for Test for a Large Multiprocessing DSP. - Graham Hetherington; Greg Sutton; Kenneth M. Butler; Theo J. Powell (ITC, 1995)

Correlating Defects to Functional and IDDQ Tests. - Theo J. Powell; James R. Pair; Bernard G. Carbajal III (ITC, 1996)

Consistently dominant fault model for tristate buffer nets. - Theo J. Powell (VTS, 1996)

A 256Meg SDRAM BIST for Disturb Test Application. - Theo J. Powell; Dan Cline; Francis Hii (ITC, 1997)

Delta Iddq for Testing Reliability. - Theo J. Powell; James R. Pair; Melissa St. John; Doug Counce (VTS, 2000)

BIST for Deep Submicron ASIC Memories with High Performance Application. - Theo J. Powell; Wu-Tung Cheng; Joseph Rayhawk; Omer Samman; Paul Policke; Sherry Lai (ITC, 2003)

Chasing subtle embedded RAM defects for nanometer technologies. - Theo J. Powell; Amrendra Kumar; Joseph Rayhawk; Nilanjan Mukherjee 001 (ITC, 2005)

Reducing Design Verification Cycle Time through Testbench Redundancy. - Aman Kokrady; Theo J. Powell; S. Ramakrishnan (VLSI Design, 2006)