Live demonstration: Real-time wavelet spike detection with in-vitro biological signals. - Adam Quotb; Jean-Baptiste Floderer; Théotime Bollengier; Rémi Fabre; Sylvie Renaud; Yannick Bornat (BioCAS, 2012)

A prototyping platform for virtual reconfigurable units. - Loïc Lagadec; Jean-Christophe Le Lann; Théotime Bollengier (ReCoSoC, 2014)

Demo: Overlay architectures for heterogeneous FPGA cluster management. - Théotime Bollengier; Mohamad Najem; Jean-Christophe Le Lann; Loïc Lagadec (DASIP, 2016)

Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach. - Théotime Bollengier; Loïc Lagadec; Mohamad Najem; Jean-Christophe Le Lann; Pierre Guilloux (ARC, 2017)

Extended overlay architectures for heterogeneous FPGA cluster management. - Mohamad Najem; Théotime Bollengier; Jean-Christophe Le Lann; Loïc Lagadec (J. Syst. Archit., 2017)

An Integrated Toolchain for Overlay-centric System-on-chip. - Jean-Christophe Le Lann; Théotime Bollengier; Mohamad Najem; Loïc Lagadec (ReCoSoC, 2018)

Du Prototypage à l'Exploitation d'Overlays FPGA. (From prototyping to exploitation of FPGA overlays). - Théotime Bollengier (2018)

Prototyping FPGA through overlays. - Théotime Bollengier; Loïc Lagadec; Ciprian Teodorov (RSP, 2021)

Secured-by-design systems-on-chip: a MBSE Approach. - Raphaële Milan; Loïc Lagadec; Théotime Bollengier; Lilian Bossuet; Ciprian Teodorov (RSP, 2023)

A New Interval Arithmetic to Generate the Complementary of Contractors. - Pierre Filiol; Théotime Bollengier; Luc Jaulin; Jean-Christophe Le Lann (Acta Cybern., 2024)

RISC-V Based Hardware Acceleration of Interval Contractor Primitives in the Context of Mobile Robotics. - Pierre Filiol; Théotime Bollengier; Luc Jaulin; Jean-Christophe Le Lann (Acta Cybern., 2024)

Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC. - Raphaële Milan; Lilian Bossuet; Loïc Lagadec; Carlos Andres Lara-Nino; Brice Colombier; Théotime Bollengier (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)