Hardware Implementation of High Throughput RC4 algorithm. - Thi Hong Tran; Leonardo Lanante; Yuhei Nagao; Masayuki Kurosaki; Hiroshi Ochi (ISCAS, 2012)

Hardware Design of Multi Gbps RC4 Stream Cipher. - Thi Hong Tran; Leonardo Lanante; Yuhei Nagao; Hiroshi Ochi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A design of low complex log likelihood ratio for MIMO decoder using the bit shift. - Reina Hongyo; Thi Hong Tran; Leonardo Lanante; Hiroshi Ochi; Yuhei Nagao (APCCAS, 2014)

A 4 × 4 multiplier-divider-less K-best MIMO decoder up to 2.7 Gbps. - Thi Hong Tran; Hiroshi Ochi; Yuhei Nagao (ISCAS, 2014)

ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac. - Thi Hong Tran; Yuhei Nagao; Hiroshi Ochi; Masayuki Kurosaki (ISCIT, 2014)

A 2D Sorter-Based K-Best Algorithm for High Order Modulation MIMO Systems. - Thi Hong Tran; Hiroshi Ochi; Yuhei Nagao (VTC Fall, 2014)

Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder. - Thi Hong Tran; Yuhei Nagao; Hiroshi Ochi (EURASIP J. Wirel. Commun. Netw., 2014)

ASIC design of a low-complexity K-best Viterbi decoder for IoT applications. - Hiromasa Kato; Thi Hong Tran; Yasuhiko Nakashima (APCCAS, 2016)

ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system. - Thi Hong Tran; Soichiro Kanagawa; Duc Phuc Nguyen; Yasuhiko Nakashima (COOL Chips, 2016)

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. - Hiromasa Kato; Satoshi Shimaya; Keisuke Fujimoto; Tomoya Kameda; Thi Hong Tran; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (CANDAR, 2016)

A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes. - Duc Phuc Nguyen; Thi Hong Tran; Yasuhiko Nakashima (J. Commun., 2017)

A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract. - Hoai Luan Pham; Thi Hong Tran; Yasuhiko Nakashima (GLOBECOM Workshops, 2018)

Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver. - Duc Phuc Nguyen; Dinh-Dung Le; Thi Hong Tran; Huu-Thuan Huynh; Yasuhiko Nakashima (CoRR, 2018)

Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems. - Dinh-Dung Le; Duc Phuc Nguyen; Thi Hong Tran; Yasuhiko Nakashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach. - Dinh-Dung Le; Duc Phuc Nguyen; Thi Hong Tran; Yasuhiko Nakashima (APCC, 2019)

Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract. - Van-Cam Nguyen; Hoai-Luan Pham; Thi Hong Tran; Huu-Thuan Huynh; Yasuhiko Nakashima (IEEE ICBC, 2019)

Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah. - Dai Long Hoang; Thi Hong Tran; Yasuhiko Nakashima (ICCBN, 2019)

Hardware Implementation of the Efficient SOR-Based Massive MIMO Detection for Uplink. - Chong Nhat Cuong; Thi Hong Tran; Duc Khai Lam (RIVF, 2019)

Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems. - Duc Phuc Nguyen; Dinh-Dung Le; Thi Hong Tran; Yasuhiko Nakashima (CoRR, 2019)

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining. - Hoai Luan Pham; Thi Hong Tran; Tri Dung Phan; Vu Trung Duong Le; Duc Khai Lam; Yasuhiko Nakashima (IEEE Access, 2020)

High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. - Van Dai Phan; Hoai Luan Pham; Thi Hong Tran; Yasuhiko Nakashima (COOL CHIPS, 2021)

MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security. - Vu Trung Duong Le; Thi Hong Tran; Hoai Luan Pham; Duc Khai Lam; Yasuhiko Nakashima (IEEE Access, 2021)

A High-Performance Multimem SHA-256 Accelerator for Society 5.0. - Thi Hong Tran; Hoai Luan Pham; Yasuhiko Nakashima (IEEE Access, 2021)

BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks. - Thi Hong Tran; Hoai Luan Pham; Tri Dung Phan; Yasuhiko Nakashima (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration. - Hoai Luan Pham; Thi Hong Tran; Vu Trung Duong Le; Yasuhiko Nakashima (IPDPS Workshops, 2022)

A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks. - Pham Hoai Luan; Thi Hong Tran; Vu Trung Duong Le; Yasuhiko Nakashima (MWSCAS, 2022)

CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. - Vu Trung Duong Le; Pham Hoai Luan; Thi Hong Tran; Yasuhiko Nakashima (SBCCI, 2022)

A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. - Pham Hoai Luan; Thi Hong Tran; Vu Trung Duong Le; Yasuhiko Nakashima (SBCCI, 2022)

A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator. - Hoai Luan Pham; Thi Hong Tran; Vu Trung Duong Le; Yasuhiko Nakashima (IEEE Access, 2022)

Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator. - Hoai Luan Pham; Thi Hong Tran; Vu Trung Duong Le; Yasuhiko Nakashima (IEEE Access, 2022)

Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. - Vu Trung Duong Le; Hoai Luan Pham; Thi Hong Tran; Thi Sang Duong; Yasuhiko Nakashima (candar, 2023)

Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications. - Vu Trung Duong Le; Hoai Luan Pham; Thi Hong Tran; Quoc Duy Nam Nguyen; Thi Sang Duong; Yasuhiko Nakashima (ICICDT, 2023)

Optimizing Parkinson's Disease Classification and Severity Assessment Using Dense Multiscale Sample Entropy and Hybrid Feature Selection. - Quoc Duy Nam Nguyen; Thi Hong Tran; Tadashi Nakano (ICIT, 2023)

Robust Deep Learning Approaches for Wireless Communication Systems. - Van Duy Tran; Duc Khai Lam; Thi Hong Tran (ICIT, 2023)

RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. - Vu Trung Duong Le; Hoai Luan Pham; Thi Sang Duong; Thi Hong Tran; Quoc Duy Nam Nguyen; Yasuhiko Nakashima (KSE, 2023)

Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. - Thi Sang Duong; Hoai Luan Pham; Vu Trung Duong Le; Thi Diem Tran; Ren Imamura; Quoc Duy Nam Nguyen; Thi Hong Tran; Yasuhiko Nakashima (MCSoC, 2023)

High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing. - Vu Trung Duong Le; Hoai Luan Pham; Thi Hong Tran; Thi Sang Duong; Yasuhiko Nakashima (MCSoC, 2023)

Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain. - Pham Hoai Luan; Thi Sang Duong; Vu Trung Duong Le; Thi Hong Tran; Yasuhiko Nakashima (MWSCAS, 2023)

Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing. - Thi Sang Duong; Hoai Luan Pham; Vu Trung Duong Le; Ren Imamura; Thi Hong Tran; Yasuhiko Nakashima (RIVF, 2023)

Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. - Thi Sang Duong; Hoai Luan Pham; Vu Trung Duong Le; Thi Hong Tran; Yasuhiko Nakashima (SOCC, 2023)

Hardware-Based Architecture for DNN Wireless Communication Models. - Van Duy Tran; Duc Khai Lam; Thi Hong Tran (Sensors, 2023)

A Decentralized COVID-19 Vaccine Tracking System Using Blockchain Technology. - Atsuki Koyama; Van Chuong Tran; Manato Fujimoto; Vo Nguyen Quoc Bao; Thi Hong Tran (Cryptogr., 2023)

Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications. - Hoai Luan Pham; Thi Hong Tran; Vu Trung Duong Le; Yasuhiko Nakashima (IEEE Des. Test, 2023)

MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. - Pham Hoai Luan; Hai Hau Nguyen; Vu Trung Duong Le; Thi Diem Tran; Tuan Hai Vu 001; Thi Hong Tran; Yasuhiko Nakashima (COOL CHIPS, 2024)

Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications. - Vu Trung Duong Le; Hoai-Luan Pham; Thi Hong Tran; Yasuhiko Nakashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications. - Vu Trung Duong Le; Hoai Luan Pham; Thi Hong Tran; Van Duy Tran; Tuan Hai Vu 001; Yasuhiko Nakashima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)