A unified {2n-1, 2n, 2n+1} RNS scaler with dual scaling constants. - Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (APCCAS, 2012)

A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. - Joshua Yung Lih Low; Ching-Chuen Jong; Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2012)

A signed integer programmable power-of-two scaler for {2n-1, 2n, 2n+1} RNS. - Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2013)

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${ {2^{n}-1, 2^{n}, 2^{n}+1 }}$. - Thian Fatt Tay; Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2013)

New algorithm for signed integer comparison in four-moduli superset {2n, 2n -1, 2n +1, 2n+1-1}. - Thian Fatt Tay; Chip-Hong Chang (APCCAS, 2014)

A new algorithm for single residue digit error correction in Redundant Residue Number System. - Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2014)

A new unified modular adder/subtractor for arbitrary moduli. - Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2015)

Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS. - Thian Fatt Tay; Chip-Hong Chang; Leonel Sousa (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS. - Thian Fatt Tay; Chip-Hong Chang (IEEE Trans. Computers, 2016)

Erratum to "Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}". - Thian Fatt Tay; Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2016)

New Algorithm for Signed Integer Comparison in {2n+k, 2n-1, 2n+1, 2n±1-1} and Its Efficient Hardware Implementation. - Sachin Kumar 006; Chip-Hong Chang; Thian Fatt Tay (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)