Eliminating speed penalty in ECC protected memories. - Michael Nicolaidis; Thierry Bonnoit; Nacer-Eddine Zergainoh (DATE, 2011)

Towards a tool for implementing delay-free ECC in embedded memories. - Thierry Bonnoit; Michael Nicolaidis; Nacer-Eddine Zergainoh (ICCD, 2011)

Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study. - Thierry Bonnoit; Michael Nicolaidis; Nacer-Eddine Zergainoh (J. Electron. Test., 2013)

Robust BER estimator for DBPSK modulation. - Thierry Bonnoit; Dominique Morche; Cedric Dehos; Emeric de Foucauld (NEWCAS, 2014)

Low cost rollback to improve fault-tolerance in VLSI circuits. - Thierry Bonnoit; Nacer-Eddine Zergainoh; Michael Nicolaidis; Raoul Velazco (LASCAS, 2017)

SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. - Thierry Bonnoit; Alexandre Coelho; Nacer-Eddine Zergainoh; Raoul Velazco (LATS, 2017)

Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution. - Thierry Bonnoit; Fraidy Bouesse; Nacer-Eddine Zergainoh; Michael Nicolaidis (DATE, 2018)

Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance. - Thierry Bonnoit; Nacer-Eddine Zergainoh; Michael Nicolaidis (IEEE Trans. Very Large Scale Integr. Syst., 2018)