Securing AES Designs Against Power Analysis Attacks: A Survey. - Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Internet Things J., 2023)

SRIL: Securing Registers from Information Leakage at Register Transfer Level. - Priyanka Panigrahi; Vignesh Ravichandra Rao; Thockchom Birjit Singha; Chandan Karfa (VLSID, 2024)

Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications. - Titu Mary Ignatius; Thockchom Birjit Singha; Roy Paily Palathinkal (IEEE Access, 2024)

Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks. - Thockchom Birjit Singha; Basa Sanjana; Titu Mary Ignatius; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Analysis of S-Box Hardware Resources to Improve AES Intrinsic Security Against Power Attacks. - Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Embed. Syst. Lett., 2024)

Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks. - Vishnu Padmakumar; Titu Mary Ignatius; Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Embed. Syst. Lett., 2025)