The design of a high-performance scalable architecture for image processing applications. - C. Thomas Gray; Wentai Liu; Thomas A. Hughes; Ralph K. Cavin III (ASAP, 1990)

P3A: a partitionable parallel/pipeline architecture for real-time image processing. - C. Thomas Gray; Wentai Liu; Thomas A. Hughes; Ralph K. Cavin III; Su-Shing Chen (ICPR (2), 1990)

Unconstrained via minimization for topological multilayer routing. - Matthias F. M. Stallmann; Thomas A. Hughes; Wentai Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Theoretical and Practical Issues in CMOS Wave Pipelining. - C. Thomas Gray; Thomas A. Hughes; Sanjay Arora; Wentai Liu; Ralph K. Cavin III (VLSI, 1991)

Fast Algorithms for One-Dimensional Compaction with Jog Insertion. - Matthias F. M. Stallmann; Thomas A. Hughes (WADS, 1993)

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. - C. Thomas Gray; Wentai Liu; Wilhelmus A. M. Van Noije; Thomas A. Hughes; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1994)

A 250-MHz wave pipelined adder in 2-μm CMOS. - Wentai Liu; C. Thomas Gray; David Fan; William J. Farlow; Thomas A. Hughes; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1994)