A logic synthesis system for VHDL design descriptions. - Thomas E. Dillinger; Kathy M. McCarthy; Thomas A. Mosher; Dale R. Neumann; Randall A. Schmidt (ICCAD, 1989)

Timing Verification and Optimization for the PowerPCTM Processor Family. - Robert E. Mains; Thomas A. Mosher; Lukas P. P. P. van Ginneken; Robert F. Damiano (ICCD, 1994)