Boundary scan in board manufacturing. - Thomas A. Ziaja; Earl E. Swartzlander Jr. (J. Electron. Test., 1994)

Characterization and analysis of errors in circuit test. - Thomas A. Ziaja; Earl E. Swartzlander Jr. (DFT, 1995)

Comprehensive Modeling of VLSI Test. - Thomas A. Ziaja; Earl E. Swartzlander Jr. (DFT, 1996)

Using LSSD to test modules at the board level. - Thomas A. Ziaja (ITC, 1999)

Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. - Kamran Zarrineh; Thomas A. Ziaja; Amitava Majumdar 002 (ICCD, 2001)

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. - Ishwar Parulkar; Thomas A. Ziaja; Rajesh Pendurkar; Anand D'Souza; Amitava Majumdar 002 (ITC, 2002)

Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. - Robert F. Molyneaux; Thomas A. Ziaja; Hong Kim; Shahryar Aryani; Sungbae Hwang; Alex Hsieh (ITC, 2007)

Transition Test on UltraSPARC- T2 Microprocessor. - Liang-Chi Chen; Paul Dickinson; Prasad Mantri; Murali M. R. Gala; Peter Dahlgren; Subhra Bhattacharya; Olivier Caty; Kevin Woodling; Thomas A. Ziaja; David Curwen; Wendy Yee; Ellen Su; et al. (ITC, 2008)

Efficient Array Characterization in the UltraSPARC T2. - Thomas A. Ziaja; Poh J. Tan (VTS, 2009)

Sparc T4: A Dynamically Threaded Server-on-a-Chip. - Manish K. Shah; Robert T. Golla; Greg Grohoski; Paul J. Jordan; Jama Barreh; Jeffrey Brooks; Mark Greenberg; Gideon Levinsky; Mark Luttrell; Christopher Olson; Zeid Samoail; Matt Smittle; et al. (IEEE Micro, 2012)