Prüfsystem VINSPEC für die automatische Qualitätssortierung von Autospiegeln. - Thomas Preußer (DAGM-Symposium, 1998)

RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. - Thomas Preußer; Steffen Köhler; Rainer G. Spallek (ESA/VLSI, 2004)

Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. - Steffen Köhler; Jens Braunes; Thomas Preußer; Martin Zabel; Rainer G. Spallek (FPL, 2004)

Design space exploration of coarse-grain reconfigurable DSPs. - Martin Zabel; Steffen Köhler; Martin Zimmerling; Thomas B. Preußer; Rainer G. Spallek (ReConFig, 2005)

Analysis of a Fully-Scalable Digital Fractional Clock Divider. - Thomas B. Preußer; Rainer G. Spallek (ASAP, 2006)

Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. - Martin Zabel; Thomas B. Preußer; Peter Reichel; Rainer G. Spallek (DSD, 2007)

Enabling constant-time interface method dispatch in embedded Java processors. - Thomas Preußer; Martin Zabel; Rainer G. Spallek (JTRES, 2007)

Bump-pointer method caching for embedded Java processors. - Thomas Preußer; Martin Zabel; Rainer G. Spallek (JTRES, 2007)

Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. - Thomas Preußer; Rainer G. Spallek (ESA, 2008)

Mapping basic prefix computations to fast carry-chain structures. - Thomas B. Preußer; Rainer G. Spallek (FPL, 2009)

High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. - Martin Zabel; Thomas B. Preußer; Rainer G. Spallek (MBMV, 2009)

An Embedded GC Module with Support for Multiple Mutators and Weak References. - Thomas B. Preußer; Peter Reichel; Rainer G. Spallek (ARCS, 2010)

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. - Thomas B. Preußer; Rainer G. Spallek (FPL, 2010)

Solving Sudokus through an incidence matrix on an FPGA. - Michael Dittrich; Thomas B. Preußer; Rainer G. Spallek (FPT, 2010)

The embedded Java benchmark suite JemBench. - Martin Schoeberl; Thomas B. Preußer; Sascha Uhrig (JTRES, 2010)

Accelerating Computations on FPGA Carry Chains by Operand Compaction. - Thomas B. Preußer; Martin Zabel; Rainer G. Spallek (IEEE Symposium on Computer Arithmetic, 2011)

Next-generation massively parallel short-read mapping on FPGAs. - Oliver Knodel; Thomas B. Preußer; Rainer G. Spallek (ASAP, 2011)

FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. - Hong Diep Nguyen; Bogdan Pasca 001; Thomas B. Preußer (FPL, 2011)

The Java Virtual Machine in retargetable, high-performance instruction set simulation. - Marco Kaufmann; Matthias Häsing; Thomas Preußer; Rainer G. Spallek (PPPJ, 2011)

Increasing the Performance and Predictability of the Code Execution on an Embedded Java Platform (Ansätze zur Steigerung der Leistungsfähigkeit und Vorhersagbarkeit der Codeausführung auf einer eingebetteten Java-Plattform). - Thomas B. Preußer (2011)

Short-Read Mapping by a Systolic Custom FPGA Computation. - Thomas B. Preußer; Oliver Knodel; Rainer G. Spallek (FCCM, 2012)

Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. - Martin Zabel; Thomas B. Preußer; Rainer G. Spallek (JTRES, 2012)

Weasel: A platform-independent streaming-optimized SATA controller. - Patrick Lehmann 001; Thomas Frank; Oliver Knodel; Steffen Köhler; Thomas B. Preußer; Rainer G. Spallek (FPL, 2013)

Ready PCIe data streaming solutions for FPGAs. - Thomas B. Preußer; Rainer G. Spallek (FPL, 2014)

PoC-align: An open-source alignment accelerator using FPGAs. - Thomas B. Preußer; Oliver Knodel; Rainer G. Spallek (ReConFig, 2014)

An LZ77-style bit-level compression for trace data compaction. - Kai-Uwe Irrgang; Thomas B. Preußer (FPL, 2015)

Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. - Kai-Uwe Irrgang; Thomas B. Preußer; Rainer G. Spallek (GI-Jahrestagung, 2015)

The portable open-source IP core and utility library PoC. - Thomas B. Preußer; Martin Zabel; Patrick Lehmann 001; Rainer G. Spallek (ReConFig, 2016)

Survey on and re-evaluation of wide adder architectures on FPGAs. - Thomas B. Preußer; Markus Krause (ReConFig, 2016)

Design Kernel Exploration Using QBF-Based Boolean Matching. - Thomas B. Preußer; Fredo Erxleben (SiPS, 2016)

Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. - Patrick Russell; Jens Döge; Christoph Hoppe; Thomas B. Preußer; Peter Reichel; Peter Schneider (DDECS, 2017)

Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs. - Thomas B. Preußer (FPL, 2017)

Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. - Michaela Blott; Thomas B. Preußer; Nicholas J. Fraser; Giulio Gambardella; Kenneth O'Brien; Yaman Umuroglu; Miriam Leeser (ICCD, 2017)

Putting Queens in Carry Chains, N o̱27. - Thomas B. Preußer; Matthias R. Engelhardt (J. Signal Process. Syst., 2017)

Inference of quantized neural networks on heterogeneous all-programmable devices. - Thomas B. Preußer; Giulio Gambardella; Nicholas J. Fraser; Michaela Blott (DATE, 2018)

A Brute-Force Solution to the 27-Queens Puzzle Using a Distributed Computation. - Thomas Preußer (Int. Conf. on Membrane Computing, 2018)

QBM - Mapping User-Specified Functions to Programmable Logic through a QBF Satisfiability Problem. - Thomas B. Preußer (CoRR, 2018)

FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. - Michaela Blott; Thomas B. Preußer; Nicholas J. Fraser; Giulio Gambardella; Kenneth O'Brien; Yaman Umuroglu (CoRR, 2018)

FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. - Michaela Blott; Thomas B. Preußer; Nicholas J. Fraser; Giulio Gambardella; Kenneth O'Brien; Yaman Umuroglu; Miriam Leeser; Kees A. Vissers (ACM Trans. Reconfigurable Technol. Syst., 2018)

The CEDARtools Platform - Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns. - Thomas Preußer; Alexander Weiss (FPL, 2019)

Test und Fehlersuche in komplexen Autonomen Systemen. - Thomas Preußer; Albert Schulz; Alexander Weiss; Martin Heininger; Martin Leucker; Malte Schmitz 001; Torben Scheffel; Daniel Thoma (Echtzeit, 2019)

An easy counting lemma. - Matthias R. Engelhardt; Thomas B. Preußer (Discret. Appl. Math., 2019)

Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. - Yaman Umuroglu; Davide Conficconi; Lahiru Rasnayake; Thomas B. Preußer; Magnus Själander (ACM Trans. Reconfigurable Technol. Syst., 2019)

HyperLogLog Sketch Acceleration on FPGA. - Amit Kulkarni 002; Monica Chiosa; Thomas B. Preußer; Kaan Kara; David Sidler; Gustavo Alonso (FPL, 2020)

Using DSP Slices as Content-Addressable Update Queues. - Thomas B. Preußer; Monica Chiosa; Alexander Weiss; Gustavo Alonso (FPL, 2020)

MicroRec: Accelerating Deep Recommendation Systems to Microseconds by Hardware and Data Structure Solutions. - Wenqi Jiang 001; Zhenhao He; Shuai Zhang 007; Thomas B. Preußer; Kai Zeng 002; Liang Feng; Jiansong Zhang 001; Tongxuan Liu; Yong Li 020; Jingren Zhou 001; Ce Zhang 001; Gustavo Alonso (CoRR, 2020)

MicroRec: Efficient Recommendation Inference by Hardware and Data Structure Solutions. - Wenqi Jiang 001; Zhenhao He; Shuai Zhang 007; Thomas B. Preußer; Kai Zeng 002; Liang Feng; Jiansong Zhang 001; Tongxuan Liu; Yong Li 020; Jingren Zhou 001; Ce Zhang 001; Gustavo Alonso (MLSys, 2021)

Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems. - Alexander Weiss; Smitha Gautham; Athira Varma Jayakumar; Carl R. Elks; D. Richard Kuhn; Raghu N. Kacker; Thomas B. Preußer (Computer, 2021)

SKT: A One-Pass Multi-Sketch Data Analytics Accelerator. - Monica Chiosa; Thomas Preußer; Gustavo Alonso (Proc. VLDB Endow., 2021)

Everything You Always Wanted to Know About Embedded Trace. - Thomas B. Preußer; Smitha Gautham; Abhi D. Rajagopala; Carl R. Elks; Alexander Weiss (Computer, 2022)

Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs. - Shivam Aggarwal; Alessandro Pappalardo; Hans Jakob Damsgaard; Giuseppe Franco; Thomas B. Preußer; Michaela Blott; Tulika Mitra (CoRR, 2023)

AMNES: Accelerating the computation of data correlation using FPGAs. - Monica Chiosa; Thomas B. Preußer; Michaela Blott; Gustavo Alonso (Proc. VLDB Endow., 2023)

On the RTL Implementation of FINN Matrix Vector Unit. - Syed Asad Alam; David Gregg; Giulio Gambardella; Thomas B. Preußer; Michaela Blott (ACM Trans. Embed. Comput. Syst., 2023)

Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs. - Shivam Aggarwal; Hans Jakob Damsgaard; Alessandro Pappalardo; Giuseppe Franco; Thomas B. Preußer; Michaela Blott; Tulika Mitra (FPL, 2024)

High-efficiency Compressor Trees for Latest AMD FPGAs. - Konstantin Hoßfeld; Hans Jakob Damsgaard; Jari Nurmi; Michaela Blott; Thomas B. Preußer (ACM Trans. Reconfigurable Technol. Syst., 2024)

FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs. - Shashwat Khandelwal; Jakoba Petri-Koenig; Thomas B. Preußer; Michaela Blott; Shreejith Shanker (CoRR, 2025)

Parallel Accurate Minifloat MACCs for Neural Network Inference on Versal FPGAs. - Hans Jakob Damsgaard; Konstantin Hoßfeld; Jari Nurmi; Thomas B. Preußer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)