A comparison of via-programmable gate array logic cell circuits. - Thomas C. P. Chau; Philip Heng Wai Leong; Sam M. H. Ho; Brian P. W. Chan; Steve C. L. Yuen; Kong-Pang Pun; Oliver C. S. Choy; Xinan Wang (FPGA, 2009)

A detailed delay path model for FPGAs. - Eddie Hung; Steven J. E. Wilton; Haile Yu; Thomas C. P. Chau; Philip Heng Wai Leong (FPT, 2009)

Generation of Synthetic Floating-Point benchmark circuits. - Thomas C. P. Chau; S. Man Ho Ho; Philip Heng Wai Leong; Peter Zipf; Manfred Glesner (IPDPS, 2009)

Rapid prototyping on a structured ASIC fabric. - Steve C. L. Yuen; Yanqing Ai; Brian P. W. Chan; Thomas C. P. Chau; Sam M. H. Ho; Oscar K. L. Lau; Kong-Pang Pun; Philip Heng Wai Leong; Oliver C. S. Choy (ASP-DAC, 2010)

Design of a single layer programmable Structured ASIC library. - Thomas C. P. Chau; David W. L. Wu; Yanqing Ai; Brian P. W. Chan; Sam M. H. Ho; Oscar K. L. Lau; Steve C. L. Yuen; Kong-Pang Pun; Oliver C. S. Choy; Philip Heng Wai Leong (DDECS, 2010)

Structured ASIC: Methodology and comparison. - Sam M. H. Ho; Steve C. L. Yuen; Hiu Ching Poon; Thomas C. P. Chau; Yanqing Ai; Philip Heng Wai Leong; Oliver C. S. Choy; Kong-Pang Pun (FPT, 2010)

Adaptive Sequential Monte Carlo approach for real-time applications. - Thomas C. P. Chau; Wayne Luk; Peter Y. K. Cheung; Alison Eele; Jan M. Maciejowski (FPL, 2012)

Roberts: reconfigurable platform for benchmarking real-time systems. - Thomas C. P. Chau; Wayne Luk; Peter Y. K. Cheung (SIGARCH Comput. Archit. News, 2012)

Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. - Thomas C. P. Chau; Xinyu Niu; Alison Eele; Wayne Luk; Peter Y. K. Cheung; Jan M. Maciejowski (ARC, 2013)

Parallelisation of Sequential Monte Carlo for real-time control in air traffic management. - Alison Eele; Jan M. Maciejowski; Thomas Chau 001; Wayne Luk (CDC, 2013)

Automating Elimination of Idle Functions by Run-Time Reconfiguration. - Xinyu Niu; Thomas C. P. Chau; Qiwei Jin; Wayne Luk; Qiang Liu 011 (FCCM, 2013)

Automating resource optimisation in reconfigurable design (abstract only). - Xinyu Niu; Thomas C. P. Chau; Qiwei Jin; Wayne Luk; Qiang Liu 011 (FPGA, 2013)

Acceleration of real-time Proximity Query for dynamic active constraints. - Thomas C. P. Chau; Ka-Wai Kwok; Gary C. T. Chow; Kuen Hung Tsoi; Kit-Hang Lee; Zion Tse; Peter Y. K. Cheung; Wayne Luk (FPT, 2013)

Accelerating sequential Monte Carlo method for real-time air traffic management. - Thomas C. P. Chau; James Stanley Targett; Marlon Wijeyasinghe; Wayne Luk; Peter Y. K. Cheung; Benjamin Cope; Alison Eele; Jan M. Maciejowski (SIGARCH Comput. Archit. News, 2013)

Architecture and Design Flow for a Highly Efficient Structured ASIC. - S. Man Ho Ho; Yanqing Ai; Thomas Chun-Pong Chau; Steve C. L. Yuen; Oliver Chiu-sing Choy; Philip Heng Wai Leong; Kong-Pang Pun (IEEE Trans. Very Large Scale Integr. Syst., 2013)

SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. - Thomas C. P. Chau; Maciej Kurek; James Stanley Targett; Jake Humphrey; Georgios Skouroupathis; Alison Eele; Jan M. Maciejowski; Benjamin Cope; Kathryn Cobden; Philip Heng Wai Leong; Peter Y. K. Cheung; Wayne Luk (FCCM, 2014)

Automating Optimization of Reconfigurable Designs. - Maciej Kurek; Tobias Becker; Thomas C. P. Chau; Wayne Luk (FCCM, 2014)

Optimising reconfigurable systems for real-time applications. - Thomas Chun-Pong Chau (2014)

Recursive pipelined genetic propagation for bilevel optimisation. - Shengjia Shao; Liucheng Guo; Ce Guo; Thomas C. P. Chau; David B. Thomas; Wayne Luk; Stephen Weston (FPL, 2015)

Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. - Thomas C. P. Chau; Xinyu Niu; Alison Eele; Jan M. Maciejowski; Peter Y. K. Cheung; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2015)

Automating Elimination of Idle Functions by Runtime Reconfiguration. - Xinyu Niu; Thomas C. P. Chau; Qiwei Jin; Wayne Luk; Qiang Liu 011; Oliver Pell (ACM Trans. Reconfigurable Technol. Syst., 2015)

An FPGA-based platform for integrated power and motion control. - Ben P. Jeppesen; Andrew Crosland; Thomas Chau 001 (IECON, 2016)

Hardware-in-the-loop simulation of FPGA-based state estimators for electric vehicle batteries. - Rocco Morello; Federico Baronti; X. Tian; Thomas Chau 001; Roberto Di Rienzo; Roberto Roncella; B. P. Jeppesen; W. H. Lin; T. Ikushima; Roberto Saletti (ISIE, 2016)

Chapter Two - Advances in Dataflow Systems. - Thomas Chau 001; Pavel Burovskiy; Michael J. Flynn; Wayne Luk (Adv. Comput., 2017)

Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control. - Shengjia Shao; Jason Tsai; Michal Mysior; Wayne Luk; Thomas Chau 001; Alexander Warren; Ben Jeppesen (ASAP, 2018)

Transparent Heterogeneous Cloud Acceleration. - Jessica Vandebon; José Gabriel F. Coutinho; Wayne Luk; Thomas Chau 001 (ASAP, 2019)

Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. - Mohamed S. Abdelfattah; Lukasz Dudziak; Thomas Chau 001; Royson Lee; Hyeji Kim; Nicholas D. Lane (DAC, 2020)

Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search. - Mohamed S. Abdelfattah; Lukasz Dudziak; Thomas Chau 001; Royson Lee; Hyeji Kim; Nicholas D. Lane (FPGA, 2020)

BRP-NAS: Prediction-based NAS using GCNs. - Lukasz Dudziak; Thomas Chau 001; Mohamed S. Abdelfattah; Royson Lee; Hyeji Kim; Nicholas D. Lane (NeurIPS, 2020)

NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition. - Abhinav Mehrotra; Alberto Gil C. P. Ramos; Sourav Bhattacharya; Lukasz Dudziak; Ravichander Vipperla; Thomas Chau 001; Mohamed S. Abdelfattah; Samin Ishtiaq; Nicholas Donald Lane (ICLR, 2021)

Zero-Cost Proxies Meet Differentiable Architecture Search. - Lichuan Xiang; Lukasz Dudziak; Mohamed S. Abdelfattah; Thomas Chau 001; Nicholas D. Lane; Hongkai Wen 001 (CoRR, 2021)

Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. - Hongxiang Fan; Thomas Chau 001; Stylianos I. Venieris; Royson Lee; Alexandros Kouris; Wayne Luk; Nicholas D. Lane; Mohamed S. Abdelfattah (MICRO, 2022)

BLOX: Macro Neural Architecture Search Benchmark and Algorithms. - Thomas Chau 001; Lukasz Dudziak; Hongkai Wen 001; Nicholas D. Lane; Mohamed S. Abdelfattah (NeurIPS, 2022)

Zero-Cost Operation Scoring in Differentiable Architecture Search. - Lichuan Xiang; Lukasz Dudziak; Mohamed S. Abdelfattah; Thomas C. P. Chau; Nicholas D. Lane; Hongkai Wen 001 (AAAI, 2023)